High-power Multilevel Converters Research Articles

Topological Analysis and Solar Grid-Tied Integration of Level Building Network Based Extendable High Power Multilevel Converter

This paper presents a new solar multilevel converter (SMLC) with closed-loop control to integrate solar PV arrays with medium voltage 3.3 kV grid. This multilevel converter produces higher number of levels in the output voltage with less usage of semiconductor switches. This solar converter utilizes only ten switches and three PV sources with equal voltage to have seven levels in the output voltage. The main motive is to have minimum switches, which reduces the count of driver circuits for a power converter. Moreover, a reduced switch converter requires less space in terms of installing the power and auxiliary components. This solar power converter comprises a solar photovoltaic (SPV) array fed level building network (LBN) nested within the six switches connected in a rectangular arrangement. The converter has two PV sources at its upper and lower ends. This solar converter is also ideal for asymmetric configurations. Moreover, the increase in solar input power is possible with more count of the LBNs. The converter switching states and operating path demonstrate the working operation of the new solar PV system. A comparison of the proposed solar converter is made with existing multilevel topologies. The system is modeled and executed in closed-loop control to showcase its effectiveness for solar power conversion. The solar converter transfers the power in varying solar conditions successfully.

Space Vector Modulation in the 45° Coordinates α′β′ for Multilevel Converters

Space vector modulation (SVM) strategy is widely used in two-level and three-level converters because of its advantages. However, the sector triangles, switching states, and switching sequences increase dramatically as the number of levels increases, which makes it difficult to implement the SVM algorithm in industrial applications of high-voltage and high-power multilevel converters. To extend the SVM strategy to high-voltage and high-power converters, a new SVM algorithm is proposed in this article with the 45° coordinates α'β'. In the α'β' coordinates, based on the relationship between the phase voltage and the line voltage of a star-connected converter, the reference vectors calculated from phase-voltage reference signals are directly used as line-voltage reference vectors. Moreover, two line-voltage levels are used as two components of the space vector, with the sum of these two components being the third line-voltage level. These three components are directly used as the switching state signals of the control line voltages. The proposed method avoids the 2/3 conversion that must be completed in the conventional SVM algorithm and does not need to calculate redundant switching states. It greatly simplifies the SVM algorithm and ensures that the common-mode voltage of the converter is zero. Finally, the proposed algorithm is validated with extensive experimental results.

Medium Voltage–High Power Converter Topologies Comparison Procedure, for a 6.6 kV Drive Application Using 4.5 kV IGBT Modules

This paper presents a general comparison procedure for medium voltage - high power multilevel converter topologies and semiconductors, which is mainly based on analyzing the performance limits of the converters output characteristics such as the output voltage, current, active power, efficiency, etc. Afterwards, the general procedure is applied to compare some of the most relevant converter topologies oriented to a 6.6 kV drive application supplying quadratic torque loads and using 4.5 kV IGBT modules. The paper concludes evaluating the comparison factors of the different converter topologies and selected semiconductors obtained by the proposed procedure. The proposed procedure can potentially be extrapolated to any desired application framework.

A Novel Switching Sequence Design for Five-Level NPC/H-Bridge Inverters With Improved Output Voltage Spectrum and Minimized Device Switching Frequency

This paper presents a novel switching sequence design for the space-vector modulation of high-power multilevel converters. The switching sequences are optimized for the improvement of harmonic spectrum and the minimization of device switching frequency. Compared to other commonly used switching sequences, the output spectrum of the proposed design shows higher inverter equivalent switching frequency. Meanwhile, the device switching frequency is reduced by using a flexible switching pattern. The proposed switching sequence has been simulated and experimentally tested on a 5-level neutral point clamped H-bridge based inverter. The results from both simulations and experiments consistently verify the above-mentioned features.