High-performance Polycrystalline Silicon Thin Film Research Articles

High-Performance Polycrystalline Silicon Thin-Film Transistors with Two-Dimensional Location Control of the Grain Boundary via Excimer Laser Crystallization

High-performance low-temperature polycrystalline silicon (Poly-Si) thin-film transistors (TFTs) have been fabricated with two-dimensional (2-D) location-controlled grain boundaries using excimer laser crystallization (ELC). By locally increased thickness of the amorphous silicon (a-Si) film that was served as the seed crystals with a partial-melting crystallization scheme, the cross-shaped grain boundary structures were produced between the thicker a-Si grids. The Poly-Si TFTs with one parallel and one perpendicular grain boundary along the channel direction could therefore be fabricated to reach excellent field-effect mobility of 530 cm2/V-s while the conventional ones exhibited field-effect mobility of 198 cm2/V-s. Furthermore, the proposed TFTs achieved not only superior electric properties but also improved uniformity as compared with the conventional ones owing to the artificially controlled locations of grain boundaries.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors by ink-jet printed nickel-mediated lateral crystallization

High-performance polycrystalline silicon thin film transistors (poly-Si TFTs) were fabricated by using ink-jet printed nickel on large area glass substrates. Direct-printed Ni dots were used as a catalyst to crystallize the amorphous silicon into poly-Si for use in the channel region of TFT devices by metal-induced lateral crystallization. The fabricated poly-Si TFTs showed high field-effect mobility and on-off ratio that are comparable to the TFTs prepared using conventional semiconductor processes. The method presented here is a combination of bottom-up and top-down approaches and has a potential to be used in next generation high-performance poly-Si TFT fabrication.

High-Performance Polycrystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process

High-performance polycrystalline silicon thin-film transistors with a low trap density at the gate-SiO2/Si interface have been developed using a low-temperature process. It was found that high-performance thin-film transistors with a very low subthreshold swing could be achieved by applying postmetallization annealing at the end of the transistor fabrication. The subthreshold swing and electron mobility of the transistors were 143 mV/dec and 262 cm2 V-1 s-1, respectively, when the thickness of the gate-SiO2 was 114 nm. The ability to fabricate such high-performance thin-film transistors on a glass substrate will be very useful for realizing system-on-panel devices.

High-Performance Polycrystalline Silicon Thin-Film Transistors Fabricated by High-Temperature Process with Excimer Laser Annealing

Polycrystalline silicon (p-Si) thin-film transistors (TFTs) were fabricated using a high-temperature process that included solid-phase crystallization (SPC) and dry thermal oxidation with excimer laser annealing (ELA). X-ray diffraction and transmission electron microscopy analyses showed that the ELA process improved the quality of p-Si films markedly. The p-Si TFTs exhibited a higher performance than the SPC and a-Si+ELA p-Si TFTs. The field-effect mobility for n-type self-aligned TFTs was 251 cm2·V-1·s-1. The longitudinal junction diffusion length of the p-Si TFTs was shorter than that of the SPC p-Si TFTs. This is favorable for fine design rules. This fabrication process is consistent with the high-temperature-processed p-Si TFT development trend towards using large substrates, low temperatures, and fine design rules.

A high-performance polycrystalline silicon thin film transistor with a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN/sub x/) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN/sub x/ and laser annealed poly-Si. After patterning thin a-Si:H/SiN/sub x/ layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250/spl deg/C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n/sup +/ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm/sup 2//Vs and a threshold voltage of 1 V.

Low-temperature dopant activation and its application to polycrystalline silicon thin film transistors

Low-temperature activation of dopants in amorphous silicon films was achieved by a new method and high-performance polycrystalline silicon thin film transistors were fabricated through its application. It was found that the dopants implanted into amorphous silicon were activated simultaneously with the crystallization of amorphous silicon. With the help of a thin nickel layer, the thermal budget for dopant activation and crystallization was considerably reduced, from 600 °C (30 h) to 500 °C (5 h). Even without plasma hydrogenation, the n-channel polycrystalline silicon thin film transistors fabricated at temperatures below 500 °C showed a mobility of 120 cm2/V s, which is much higher than that of conventional devices fabricated at 600 °C.