High Performance Optical Interconnects Research Articles

Evaluation of the coupling characteristics of a sandwiched plasmonic waveguide between two dielectric waveguides using air-gap couplers to achieve high-performance optical interconnects

To achieve ultrahigh-density nanoplasmonic integrated circuits, low-loss conventional dielectric waveguides (CDWs) are used to transfer light into and out of the metal–dielectric–metal (MDM) plasmonic waveguides. We show that sandwiching the MDM plasmonic waveguide between two CDWs forms a Fabry–Perot cavity-like structure, which causes oscillations in the transmission coupling efficiency (TCE) into the output CDW as the length of the MDM waveguide is increased. Three types of compact air-gap couplers (AGCs) were used at the interface between those two types of waveguides to enhance the coupling efficiency between them. Our simulation results indicate that tapering CDW before it is connected to AGC not only enhances TCE into the output CDW by 9% over a wide spectrum range but also reduces the need for high-precision fabrication techniques to align AGC at the interface. Moreover, we achieved a TCE into the output CDW of 77% optimized for the optical communications wavelength of 1550 nm when the length of the MDM plasmonic waveguide is 600 nm. In addition, we showed that our proposed design has large fabrication tolerance by investigating the change in its spectrum response as various parameters of the design dimensions differ from that of the targeted optimum dimensions. We found that increasing the dimensions of AGC reduces the width of the spectrum, whereas increasing the width of CDW with its tapered part shifts the spectrum to the right by 100 nm per 40 nm increase in the width. We also found that increasing the refractive index of the MDM plasmonic waveguide with AGC controls the cutoff wavelength, in which TCE is almost zero at wavelengths shorter than the cutoff wavelength, and consequently provides a unique advantage in using our proposed design in sensing applications.

Perspectives on How the "Sige, Ge, & Related Compounds: Materials, Processing, and Devices" Field Has Changed over the Last 20 Years

The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to include work in nano-wires, nano-membranes, and light emitting structures with SiGe and/or Ge. In 2012 the symposium explored finfet devices and expanded to include the area of GeSn. In 2014 the symposium explored the use SiGe and related compounds in more complex and advanced structures. In 2016 the conference had a theme around SOI and the FDSOI technology in particular. In 2018 the themes were the ever expanding device structures and role epitaxy has played in it.Each year the plenary talks were selected to give a view of the industry and the conference. These talks give us insight into the symposium and how the field has changed over time.In 2004 the first symposium “SiGe 1: Materials, Processing, and Devices” focused on the SiGe HBT transistor performance and SiGe epitaxial technology. But CMOS scaling was also presented. These trends were reflected in the plenary talks were given by John Cressler on “Using SiGe HBTs for Mixed-Signal Circuits and Systems: Opportunities and Challenges” and Judy Hoyt on “Enhanced Mobility CMOS.” This was the first symposium and we set the conference organization with multiple topical committees and published the first proceedings.In 2006 the “SiGe and Ge 2” symposium continued the themes of SiGe and Ge Epitaxy, SiGe HBT, CMOS scalling, and added silicon photonics. The Plenary talks were given by Dimitris Antoniadis on “Channel Material Innovations for Continuing the Historical MOSFET Performance Increase with Scaling” and Cary Gunn on “CMOS Photonics for High Speed Interconnects.”In 2008 the “SiGe, Ge, & Related Compounds 3” symposium changed in composition bringing IIIV and other compounds into the symposium. The Plenary papers were by Krishna Saraswat on “Germanium for High-Performance MOSFETS and Optical Interconnects,” and Wiebe B. de Boer on “Si and SiGe Epitaxy in Perspective.” Krishna focused on the role of Ge in modern devices and Wiebe focused on the history of SiGe epitaxy at ASM.In 2010 the “SiGe, Ge, & Related Compounds 4” greatly expanded topics while maintaining the core of SiGe HBT and CMOS scaling. The plenary papers were given by K. Kuhn on “Past, Present, and Future: SiGe and CMOS Transistor Scaling” and L. Kimmerling on “Scaling Energy and Form Factor with Germanium Microphotonics.” The conference emphasis continued on SiGe epitaxy, CMOS scaling, and HBT performance with a new optoelectronics focus area.In 2012 the “SiGe, Ge, & Related Compounds 5” focused on the finfet and GeSn. The plenary papers were given by E. Nowak “Advanced CMOS scaling and FinFET Technology” and C. Hu on “FinFET and UTB – How to make very short channel MOSFETs.” There were 4 sessions containing papers with GeSn.In 2014 the “SiGe, Ge, & Related Compounds 6” returned to CMOS scaling and the SiGe HBT. The plenary papers were given by K. Uchida and T. Takahashi on “Extending the FETs: Challenges and Opportunities for New Materials and Structures” and L. Zimmermann (IHP) on “High-Performance Photonic BiCMOS – Next Generation More-than-Moore Technology for the Large Bandwidth Era.”In 2016 the “SiGe, Ge, & Related Compounds 7” focused on FDSOI. The plenary papers were given by Bruce Doris “FDSOI Past, Present and Future” and Carlos Mazure and S. Cristoloveanu “ FD-SOI: The History from Early Transistors to Today.”In 2018 the “SiGe, Ge, & Related Compounds 8” focused on CMOS scaling and SiGe as an enabling material. The plenary papers were given by Maszara, Witold on “Contemporary and Future Logic Devices” and by Tsu-Jae Liu on “ Silicon-Germanium: Enabler of Moore's Law.”In 2020 the “SiGe, Ge, & Related Compounds 9” symposium focused on III-Vs and Silicon Photonic Sensors. The plenary papers were given by N. Collaert on “The revival of compound semiconductors and how they will change the world in the 5G/6G era,” and Ben Miller on “Creating the Interface Universe between the Universe and Data with Integrated Photonic Sensors."Highlights from these plenary talks and symposium topics will be presented.

Guest Editorial Optical Interconnects

The eight papers in this special section focus on high performance optical interconnect architectures and key technologies which can support the rising bandwidth demands of mega data centers and high-performance computing systems. The papers are expanded versions of papers presented at the 2015 IEEE Optical Interconnects Conference.

Advanced modulation formats for high-performance short-reach optical interconnects.

The explosive growth of the traffic between data centers has led to an urgent demand for high-performance short-reach optical interconnects with data rate beyond 100G per wavelength and transmission distance over hundreds of kilometers. Since direct detection (DD) provides a cost-efficient solution for short-reach interconnects, various advanced modulation formats have been intensively studied to improve the performance of DD for high-performance short-reach optical interconnects. In this paper, we report the recent progress on the advanced DD modulation formats that provide superior electrical spectral efficiency (SE) and transmission reach beyond that of simple direct modulation (DM) based direct detection (DM/DD). We first provide a review of the current advanced modulation formats for high-performance short-reach optical interconnects. Among these formats, Stokes vector direct detection (SV-DD) achieves the highest electrical spectrum efficiency, presenting itself as a promising candidate for future short-reach networks. We then expound some novel algorithms to achieve high-performance SV-DD systems under severe impairments of either polarization mode dispersion (PMD) or polarization dependent loss (PDL).

(Invited) Silicon Compatible High Performance Optical Interconnect Technology

High speed optical interconnects provide significant performance improvement and power savings over copper-based solutions in high performance computing and data networking applications. APIC's integrated components using wavelength division multiplexing have been demonstrated for avionics networking. Extension of this technology to the chip scale enables multicore processors to be networked using optical interconnects, extending the performance and power benefits to large scale multicore processors. CMOS fabrication compatibility necessitates that the optical transmitters and receivers and other link components be silicon based, which we implement using epitaxial germanium. APIC has demonstrated both optical transmission and detector technology using germanium in silicon and is working on transitioning the fabrication process to a production foundry. Here we show recent results of germanium optical receivers and, more significantly, demonstration of strained germanium optical sources integrated in a silicon chip. The optical link is suitable for integrated chip-scale fabrication.

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation

As the number of IPs (processor, memory) integration on a chip increases, chip multicore processors (CMPs), and system-on-chips (SoCs) will require high performance and low power consumption interconnection infrastructure. Traditional electronic network-on-chip (NoC) faces several problems, such as limited bandwidth, crosstalk, impedance mismatch, and huge power dissipation. To alleviate these challenges, optical NoCs have emerged as an attractive solution. Optical interconnects take advantage of light, and the multiple wavelengths within a single optical link (waveguide) to achieve high communication bandwidth at low power consumption cost. Toward this work we aim to propose a cost-performance and power efficient NoC. First, we proposed a low latency path setup network for conventional hybrid electronic-photonic Torus NoC using predictive switching. By lowering the path setup latency, we could achieve a considerable performance improvement. Second, a new hybrid architecture formed of an optical ring and electrical crossbar (OREX) has been proposed. OREX reduces the path setup network to a single electrical crossbar. Its optical network uses a ring topology more adapted for photonic interconnects. Using a cycle accurate simulator, our results show that OREX further improves hybrid electronic-photonic NoCs performance. Finally, to reduce power consumption, we have proposed a fully optical ring architecture. The proposed architecture combines static and dynamic wavelength allocation in the same network to fully take advantage of the low power and high performance optical interconnects. A different wavelength-channel is statically allocated to each destination node for light weight communication. Contention of simultaneous communication requests from multiple source nodes to the destination is solved by a token based arbitration. For heavy load communication, a shared multiwavelength-channel is available by requesting it in execution time from source node to a special node that manages dynamic wavelength allocation. Our architecture takes advantage of both wavelength allocation mechanisms by selecting the adequate one, depending on iv communication message sizes (baseline) and network congestion information (contention based and smart selection). Preliminary hardware cost comparison with several photonic architecture shows that our architecture can be an attractive costperformance interconnection infrastructure for future SoCs and CMPs. We further discuss performance of the proposed fully optical ring NoC architecture based on simulation using a photonic network simulator. Results show that our architecture allows considerable reduction of the network energy consumption compared to conventional hybrid NoCs and show reasonable bandwidth and latency performance using probabilistic traffic patterns.

Developments continue for VCSEL research

In recent years the demand for high-performance low-cost optical interconnect components has accelerated. An ideal solution for the transmitter has been found with the development of the vertical-cavity surface-emitting laser (VCSEL). VCSELs show potential for many applications principally due to the ease of producing two-dimensional arrays. One of the most important properties of the VCSEL is its well-defined beam properties, such as circular geometry and its surface-normal emission. VCSELs have been the topic of intense research for several years now. This article will only look at some recently reported results in this field.

Design and analysis of single-mode oxidized VCSELs for high-speed optical interconnects

Oxide-confined vertical-cavity surface-emitting laser diodes (VCSELs) are fabricated for applications in high-performance optical interconnects. Both 980-nm as well as 850-nm wavelength devices in one- and two-dimensional arrays are investigated. Noise properties of single- and multimode devices under different operation conditions are relative intensity noise of single-mode devices can be as low as -150 dB/Hz at output powers of about 1 mW and feedback levels up to -30 dB. Data rates up to 12.5 Gb/s with bit error rates below 10/sup -11/ are achieved with VCSELs showing stable single-mode emission at large-signal modulation, combined with modulation bandwidths exceeding 10 GHz. Arrays with 4/spl times/8 elements flip-chip mounted on Si CMOS driver chips ready for use in parallel data transmission systems are presented.

A low-cost high-performance optical interconnect

Summary form only given. The optical waveguides have a uniformity of 1 dB. The resulting optical links have a jitter of no more than 150 ps not including pulse-width distortion, static skew between channels of less than 200 ps and dissipate 1.5 W. A representative multichannel eye pattern at 400 Mbit/s is shown. In this presentation we focus on the design approach and subsystem requirements that make this performance possible without sacrificing manufacturability or cost.

A System Design Perspective on Optical Interconnection Technology

Demands for increased interconnection density and higher bandwidth, coupled with constraints on the cost of advanced wide-bandwidth telecommunication switching and high-throughput computer architectures, are exhausting the capabilities of conventional electrical interconnection. Advances in integrated circuit technologies and enhanced digital services have created a “bottleneck” at the circuit-board-to-circuit-board level of the interconnection hierarchy. To alleviate this problem, AT&T is developing new techniques in parallel optical interconnection. Inserting parallel optical interconnection technology into advanced electronic processing systems not only meets projected performance requirements, but also potentially offers them at a competitive cost. This paper describes how future high-performance parallel optical interconnect technology might be packaged and used.

Co-integration of optoelectronics and submicrometer CMOS

The rapid emergence of multichip modules (MCMs) and the continuing interest in wafer scale integration (WSI) provide important opportunities for successful insertion of high performance optical interconnections into real systems. The large area substrates and the distances between packaged wafer-level modules introduce distances of sufficient length that propagation of very high-speed digital signals along electrical lines will be difficult. At the same time, the substrates allow use of thin film technologies for fabrication of optoelectronic devices, optical waveguides, and other optical elements, drawing on the natural alignment accuracy of photolithographic definition of optical components to avoid several practical problems arising when optical elements are surface mounted. For such reasons, large area silicon wafers provide an important potential application for more aggressive use of optical interconnections. An important issue is growth of GaAs semiconductor regions within a silicon WSI or MCM substrate containing high performance silicon CMOS circuitry, seeking to co-integrate optical and silicon VLSI devices. Experimental studies of submicrometer CMOS device characteristics following thermal simulation of GaAs heteroepitaxial growth are summarized. >

Optical interconnection and packaging technologies for advanced avionics systems

An optical backplane developed to demonstrate the advantages of high-performance optical interconnections and supporting technologies and designed to be compatible with standard avionics racks is described. The hardware demonstrates the three basic components of optical interconnects: optical sources, an optical signal distribution network, and optical receivers. Results from characterization and environmental tests, including a demonstration of the reliable transmission of serial data at a 1 Gb/s, are reported. >