High-performance Low-power CMOS Research Articles

High performance low power CMOS temperature sensor

A temperature sensor based on the combination of a temperature variable oscillator and a linear controlled oscillator is proposed, which can realize temperature detection through the characteristic of frequency changing with temperature. The changing frequency is generated by the two oscillators, and by adjusting the frequency linear change, the linearity of the sensor is also increased. Through the frequency digitizer, the digital signal can be output. Compensation through a process compensator improves the accuracy of the sensor after a single point correction. After conducting tests on 15 experimental samples, the accuracy was achieved within ± 1.2∘C across the temperature range of 0 to 125∘C, demonstrating a highly favorable level of precision.

Introduction of New Materials into CMOS Devices

With the progress of recent smart society, demand for high-performance low-power CMOS devices becomes stronger and stronger. Corresponding to the situation, the downsizing of CMOS device has been accelerated significantly. In order to solve the problem inherent in the downsizing, new structures and new materials are being aggressively introduced into MOSFETs. They are, for example, nanowire channel, metal/high-k gate stack, metal/silicide source/drain. In this paper, the status of the new material introduction to CMOS devices is described.

High-performance micropower class AB current mirror

A novel high-performance low-power CMOS class AB current mirror is presented. The circuit combines very high linearity, very low input and high output resistance, high current handling capability and low standby power consumption. Measurement results show a THD<−85 dB for input current amplitudes five times larger than the bias current.

Design and Optimization of a High Performance Low-Power CMOS Flex Cell

Design and Optimization of a High Performance Low-Power CMOS Flex Cell

A high-performance low-power CMOS AGC for GPS application

A wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier (VGA), a comparator and a charge pump, and the dB-linear gain is controlled by the charge pump. The AGC was implemented in a 0.18 μm CMOS technology. The dynamic range of the VGA is more than 55 dB, the bandwidth is 30 MHz, and the gain error is lower than ±1.5 dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW, and the area of the AGC is 700 × 450 μm2.

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.

A high performance low power CMOS channel filter

A new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it very cost effective in telecommunication switching systems. The design of this chip, including architectural, switched capacitor filter, and amplifier considerations is described, and typical experimental results are presented.