High Performance FPGA Research Articles

Enhancing efficiency in spaceborne phased array systems: MVDR algorithm and FPGA integration

Digital Beamforming (DBF) has garnered significant attention within the space community, driven by the heightened flexibility offered by satellites equipped with active antennas for diverse applications like spaceborne synthetic aperture radar (SAR) systems and communication services. This paper presents a comprehensive exploration encompassing analysis, design, and implementation of a Minimum Variance Distortionless Response (MVDR) algorithm tailored for application in a Digital Beamforming Receiver system. The described system leverages the capabilities of the high-speed Analog to Digital Converter (ADC) device EV12AQ600, space-qualified, and the high-performance FPGA XCKU085. These components are seamlessly integrated into the EV12AQ60X-ADX-EVM evaluation board, thoughtfully provided by Teledyne e2v Semiconductors. The design methodology outlined herein is driven by the overarching objective to minimize FPGA resource utilization and power consumption for spaceborne phased array systems. This objective is chiefly met through the implementation of a systolic array structure adept at processing both real and complex input samples. This innovative approach results in a substantial reduction in allocated resources compared to conventional architectures. Furthermore, the design incorporates the use of the CORDIC algorithm to compute the inverse of the correlation matrix, obviating the need for square root and division operations. This strategic utilization of algorithms enhances the system's efficiency in terms of resource utilization, computational load, and processing time. To validate the anticipated behavior of the adaptive beamforming system, various radio frequency (RF) input signals are applied to the system, which is physically instantiated on the EV12AQ60X-ADX-EVM evaluation board. The experimental results affirm the efficacy of the proposed design, underscoring its suitability for spaceborne applications.

Design and Implementation of High-Performance FPGA Accelerator for Non-Separable Discrete Fourier Transform Optimizing Real-Time Image and Video Processing

Design and Implementation of High-Performance FPGA Accelerator for Non-Separable Discrete Fourier Transform Optimizing Real-Time Image and Video Processing

Machine Learning for Real-Time Processing of ATLAS Liquid Argon Calorimeter Signals with FPGAs

With the High-Luminosity upgrade of the LHC, the number of simultaneous proton-proton collisions will be increased to up to 200. This requires an extensive overhaul of the detector systems. For the ATLAS Liquid Argon calorimeter electronics, 556 high performance FPGAs will be installed to reconstruct the energy for all 182 468 cells at the LHC bunch crossing frequency of 40 MHz. However, the current digital filter used for energy reconstruction (optimal filter) decreases in performance under these high pileup conditions. We demonstrate, that small recurrent or convolutional neural networks can outperform the optimal filter. Prototype implementations of the respective inference code in VHDL show, that the use of these networks on FPGAs is feasible and the resulting firmware fits onto the planned Intel Agilex devices. The full design is capable of processing 384 detector cells per FPGA, by combining parallel instances of the firmware with time division multiplexing.

A novel approach to generate trigonometric functions using high performance FPGA

This paper describes the novel approach to generate the trigonometric function sine wave with different amplitudes and different frequencies. The proposed design is synthesized using Xilinx ISE 14.7 using Verilog HDL programming language and simulated using the modelsim simulator. The sine wave generation is targeted on the high performance Zynq 7-series Zedoard FPGA (7020) which has a capability of programming language (PL) and processing system (PS). Generation of sine wave is carried out using Xilinx IP Core (DDS) approach with simulation, and synthesis. Zed board works on 28nm technology. Hardware device utilization summary of the design is analyzed along with the timing values. The power report of the design is extracted using the X power analyzer. Power analysis is compared with Micro wind software and X-power analyzer.

High-precision digital time-amplitude analysis system for the neutron Time-Of-Flight spectrometer in HL-2M

Neutron time-of-flight (TOF) spectrometers are widely used for neutron diagnostics in large-scale fusion facilities. However, traditional amplitude and time analysis methods are limited in terms of resolution, flexibility, and other factors. To overcome these limitations, we propose the Digital Time-Amplitude Analysis (DTAA) system, which combines the advantages of both methods by using a high-performance FPGA for real-time time and amplitude analysis of particle pulses. The DTAA system provides accurate timing and pulse shape information, fast processing speed, and low implementation cost. We have also developed a multi-mode data joint time-of-flight correction algorithm and verified its performance through simulation. The DTAA system passed laboratory and tokamak tests, achieving a time measurement precision of 122 ps and accurately measuring neutron counts in tokamak experiments. This work represents a key step towards comprehensive high-performance integrated particle pulse analysis.

High-Performance FPGA Streaming Data Concentrator for GEM Electronic Measurement System for WEST Tokamak

The paper presents developments and significant improvements of the soft X-ray measurement system installed at the WEST tokamak. In the introduction, a brief discussion is carried out in the scope of energy shortage, fusion energy as a remedy, and the necessity of impurities monitoring in the scope of stable and long plasma discharge. This requires high-speed and accurate measurement systems due to the intense data streams that need to be processed online. For that reason, the SXR GEM FPGA-based system was designed by the Institute of Electronic Systems of the Warsaw University of Technology, the Institute of Plasma Physics and Laser Microfusion from Warsaw, and installed at the WEST tokamak in collaboration with the Institute for Magnetic Fusion Research, Commissariat à l’Énergie Atomique. It is the second-generation system, whereas the first was installed at JET tokamak. The article describes the architecture of the designed electronic part of the system. The paper presents an entirely new approach for the data concentration module implemented in FPGA. The main premise is to select only active data and send them chronologically to the embedded computer with high throughput. It is the essential component for long-term plasma operations, about 1 min, now carried out at WEST tokamak during the C3 campaign. The paper describes the laboratory tests under the exploitation of various radiation sources and the implementation of the solution and measurements during tokamak plasmas. Previous and current data acquisition methods are compared. The results show that implementing a new local trigger has significantly improved the system performance compared to the global trigger-based acquisition. The results are approximately 17 times better in the scope of performance and more than 20 times better in terms of data compression. The described design was successfully applied during the most recent 2023 experimental campaign at the WEST tokamak.

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application.

A high-performance Driver State Monitoring (DSM) application for the detection of driver drowsiness is presented in this paper. The popular Ensemble of Regression Trees (ERTs) machine learning method has been employed for the alignment of 68 facial landmarks. Open-source implementation of ERTs for facial shape alignment has been ported to different platforms and adapted for the acceleration of the frame processing speed using reconfigurable hardware. Reducing the frame processing latency saves time that can be used to apply frame-to-frame facial shape coherency rules. False face detection and false shape estimations can be ignored for higher robustness and accuracy in the operation of the DSM application without sacrificing the frame processing rate that can reach 65 frames per second. The sensitivity and precision in yawning recognition can reach 93% and 97%, respectively. The implementation of the employed DSM algorithm in reconfigurable hardware is challenging since the kernel arguments require large data transfers and the degree of data reuse in the computational kernel is low. Hence, unconventional hardware acceleration techniques have been employed that can also be useful for the acceleration of several other machine learning applications that require large data transfers to their kernels with low reusability.

The DAQPATH readout system of the Serenity boards for the CMS Phase-II Upgrade

The Serenity boards are ATCA custom boards used in the readout of the Phase-II CMS detector. Each board can handle up to 144 optical serial links (up to 25Gb/s each) and supports up to two high-performance FPGAs. In several applications the Serenity board is required to aggregate raw events (Front-End data) from the detector at every Accepted Level 1 trigger and route this event fragment to the central DAQ system. The architecture and behavior of the DAQPATH firmware that collects and merges Front-End data and manages their transmission to the DAQ system over 25Gb/s output optical links are here described. • Data, trigger, readout electronics for HEP CMS experiment. • High speed links communication. • HDL firmware design.

Real-time digital signal processing implementation for in-beam PET of radiotherapy imaging in HIMM

The in-beam positron emission tomography (ibPET) is dedicated to radiotherapy imaging of the heavy-ion medical machine (HIMM), which requires precise online measurement, as well as real-time signal processing capability of the electronics. In this paper, we present the implementation of real-time digital signal processing in the data acquisition unit (DAQU) for an ibPET system based on the photomultiplier tube (PMT) readout of lutetium-yttrium oxyorthosilicate (LYSO) scintillator crystals. We have designed 10-channel customized signal processing circuit on a high-performance FPGA, which supports 3 working modes (single event processing mode, self-calibration mode and raw ADC data mode), position calculation, crystal locating, event sorting, and etc. Moreover, the implementation of real-time corrections is capable of dealing with photon peak correction to 511 keV and crystal ID-based time correction. The implemented real-time ibPET system can achieve 46% data compression and beyond 1,000,000 events/sec/channel signal processing capabilities. A series of initial tests is conducted, and the results indicate that this design meets the application requirement on online processing.

High-precision large-area muon tracking and triggering with drift-tube chambers at future colliders

Experiments like the ATLAS detector at the HL-LHC or detectors at future hadron colliders need muon detectors with excellent momentum resolution at the percent level up to the TeV scale both at the trigger and the offline reconstruction level. This requires muon tracking chambers with high spatial resolution even at the highest background fluxes. Drift-tube chambers are the most cost effective technology for the instrumentation of large-area muon systems providing the required high rate capability and three-dimensional spatial resolution. Thanks to the advances in analog and digital electronics, modern drift-tube chambers can be used in stand-alone mode up to the highest background rates providing event times and second coordinates without the necessity of additional trigger chambers. New key developments in the integrated front-end electronics are fast baseline restoration of the shaped signal and picosecond time-to-digital converters for second coordinate measurement with double-sided read-out of the tubes. Self-triggered operation has become possible using modern high-performance FPGAs allowing for real-time pattern recognition and track reconstruction.

Research on the Lightweight Deployment Method of Integration of Training and Inference in Artificial Intelligence

In recent years, the continuous development of artificial intelligence has largely been driven by algorithms and computing power. This paper mainly discusses the training and inference methods of artificial intelligence from the perspective of computing power. To address the issue of computing power, it is necessary to consider performance, cost, power consumption, flexibility, and robustness comprehensively. At present, the training of artificial intelligence models mostly are based on GPU platforms. Although GPUs offer high computing performance, their power consumption and cost are relatively high. It is not suitable to use GPUs as the implementation platform in certain application scenarios with demanding power consumption and cost. The emergence of high-performance heterogeneous architecture devices provides a new path for the integration of artificial intelligence training and inference. Typically, in Xilinx and Intel’s multi-core heterogeneous architecture, multiple high-performance processors and FPGAs are integrated into a single chip. When compared with the current separate training and inference method, heterogeneous architectures leverage a single chip to realize the integration of AI training and inference, providing a good balance of training and inference of different targets, further reducing the cost of training and implementation of AI inference and power consumption, so as to achieve the lightweight goals of computation, and to improve the flexibility and robustness of the system. In this paper, based on the LeNet-5 network structure, we first introduced the process of network training using a multi-core CPU in Xilinx’s latest multi-core heterogeneous architecture device, MPSoC. Then, the method of converting the network model into hardware logic implementation was studied, and the model parameters were transferred from the processing system of the device to the hardware accelerator structure, composed of programmable logic through the bus interface AXI provided on the chip. Finally, the integrated implementation method was tested and verified in Xilinx MPSoC. According to the test results, the recognition accuracy of this lightweight deployment scheme on MNIST dataset and CIFAR-10 dataset reached 99.5 and 75.4% respectively, while the average processing time of the single frame was only 2.2 ms. In addition, the power consumption of the network within the SoC hardware accelerator is only 1.363 W at 100 MHz.

FPGA-Based Deep Learning Models for Analysing Corona Using Chest X-Ray Images

Coronavirus is a large family of viruses that affects humans and damages respiratory functions ranging from cold to more serious diseases such as ARDS and SARS. But the most recently discovered virus causes COVID-19. Isolation at home or hospital depends on one’s health history and conditions. The prevailing disease that might get instigated due to the existence of the virus might lead to deterioration in health. Therefore, there is a need for early detection of the virus. Recently, many works are found to be observed with the deployment of techniques for the detection based on chest X-rays. In this work, a solution has been proposed that consists of a sample prototype of an AI-based Flask-driven web application framework that predicts the six different diseases including ARDS, bacteria, COVID-19, SARS, Streptococcus, and virus. Here, each category of X-ray images was placed under scrutiny and conducted training and testing using deep learning algorithms such as CNN, ResNet (with and without dropout), VGG16, and AlexNet to detect the status of X-rays. Recent FPGA design tools are compatible with software models in deep learning methods. FPGAs are suitable for deep learning algorithms to make the design as flexible, innovative, and hardware acceleration perspective. High-performance FPGA hardware is advantageous over GPUs. Looking forward, the device can efficiently integrate with the deep learning modules. FPGAs act as a challenging substitute podium where it bridges the gap between the architectures and power-related designs. FPGA is a better option for the implementation of algorithms. The design attains 121µW power and 89 ms delay. This was implemented in the FPGA environment and observed that it attains a reduced number of gate counts and low power.

Characterization of Burst-Mode Links for Optical Circuit Switching

The performance of an optically circuit-switched network depends on the transient locking characteristics of the transceiver as a function of the received power before and after a switching event. These characteristics are not specified in current transceiver standards. Here, we present a novel characterization method to assess the transient locking characteristics of transceivers when used in an optical circuit-switched network. The method uses custom hardware code implemented on a high-performance FPGA. This code samples the bit error rate in a manner similar to a sampling oscilloscope. The output is a time-resolved bit error rate measurement on a microsecond time scale. We then use this technique to quantify the transient locking characteristics of commercial datacom transceivers as a function of the nominal received power, the power offset between the channels being switched, and the transition time of the optical switch. These results enable research into optical circuit-switched networks based on commercial datacom transceivers.

Design and Implementation of Digital Beam Former Architecture for Phased Array Radar

This paper deals with the design and implementation of a digital beam former architecture which is developed for 4/8/12/16 element phased array radar. This technique employs a very high performance FPGA to handle large no of parallel complex arithmetic operations including digital down conversion and filtering. A 3MHz echo signal riding on an IF carrier of 60 MHz is under sampled at 50 MHz and down converted digitally to bring the spectrum to echo signal baseband. After suitable decimation filtering, the I and Q channels are multiplied with Recursive Least Squares based optimized complex weights to form partial beams. The prototype architecture employs techniques of pipelining and parallelism to generate multiple beams simultaneously from a 16 element array within 1 μsec. This can be extended to several number of arrays. The critical components employed in this design are eight 16 bit 125 MS/s ADCs and a very high performance state of the art Xilinx FPGA device Virtex-5 FX 130T having several on-chip resources and 150 MHz clock generators.

High performance FPGA based secured hardware model for IoT devices

High performance FPGA based secured hardware model for IoT devices

Reduction in Total Harmonic Distortion in Induction Motor Drives with High-Performance FPGA Controller

Reduction in Total Harmonic Distortion in Induction Motor Drives with High-Performance FPGA Controller

Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects

FPGA-based accelerators are increasingly popular across a broad range of applications, because they offer massive parallelism, high energy efficiency, and great flexibility for customizations. However, difficulties in programming and integrating FPGAs have hindered their widespread adoption. Since the mid 2000s, there has been extensive research and development toward making FPGAs accessible to software-inclined developers, besides hardware specialists. Many programming models and automated synthesis tools, such as high-level synthesis, have been proposed to tackle this grand challenge. In this survey, we describe the progression and future prospects of the ongoing journey in significantly improving the software programmability of FPGAs. We first provide a taxonomy of the essential techniques for building a high-performance FPGA accelerator, which requires customizations of the compute engines, memory hierarchy, and data representations. We then summarize a rich spectrum of work on programming abstractions and optimizing compilers that provide different trade-offs between performance and productivity. Finally, we highlight several additional challenges and opportunities that deserve extra attention by the community to bring FPGA-based computing to the masses.

Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM

In this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth Memory). The geometry of the algorithm (a triangular matrix walk) and the FPGA capabilities pose two challenges. First, several replicated IPs can be instantiated in the FPGA fabric, so load balance is an issue not only at system-level (CPU+FPGA), but also at device-level (FPGA IPs). And second, the data that each one of these IPs accesses must be carefully placed among the HBM banks in order to efficiently exploit the memory bandwidth offered by the banks while optimizing power consumption.To tackle the first challenge we propose a novel hierarchical scheduler named Fastfit, to efficiently balance the workload in the heterogeneous system while ensuring near-optimal throughput. Our scheduler consists of a two level scheduling engine: (1) the system-level scheduler, which leverages an analytical model of the FPGA pipeline IPs, to find the near-optimal FPGA chunk size that guarantees optimal FPGA throughput; and (2) a geometry-aware device-level scheduler, which is responsible for the effective partitioning of the FPGA chunk into sub-chunks assigned to each FPGA IP. To deal with the second challenge we propose a methodology based on a model of the HBM bandwidth usage that allows us to set the minimum number of active banks that ensure the maximum aggregated memory bandwidth for a given number of IPs. Through exhaustive evaluation we validate the accuracy of our models, the efficiency of our intra-device partition strategies and the performance and energy efficiency of our Fastfit heterogeneous scheduler, finding that it outperforms state-of-the-art previous schedulers by achieving up to 99.4% of ideal performance.

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

As big data analytics systems are squeezing out the last bits of performance of CPUs and GPUs, the next near-term and widely available alternative industry is considering for higher performance in the data center and cloud is the FPGA accelerator. We discuss several challenges a developer has to face when designing and integrating FPGA accelerators for big data analytics pipelines. On the software side, we observe complex run-time systems, hardware-unfriendly in-memory layouts of data sets, and (de)serialization overhead. On the hardware side, we observe a relative lack of platform-agnostic open-source tooling, a high design effort for data structure-specific interfaces, and a high design effort for infrastructure. The open source Fletcher framework addresses these challenges. It is built on top of Apache Arrow, which provides a common, hardware-friendly in-memory format to allow zero-copy communication of large tabular data, preventing (de)serialization overhead. Fletcher adds FPGA accelerators to the list of over eleven supported software languages. To deal with the hardware challenges, we present Arrow-specific components, providing easy-to-use, high-performance interfaces to accelerated kernels. The components are combined based on a generic architecture that is specialized according to the application through an extensive infrastructure generation framework that is presented in this article. All generated hardware is vendor-agnostic, and software drivers add a platform-agnostic layer, allowing users to create portable implementations.

EtherCAT slave controller for AC servo motor

The EtherCAT network was developed by Beckhoff Automation and it is considered the fastest technology among industrial Ethernet networks. Thanks to high data transmission rates, flexible connectivity and nanosecond synchronization, EtherCAT networks are becoming more and more popular in industrial applications. AC Servo motors are becoming more and more popular in industrial applications due to their high efficiency, fast dynamic response, low noise and high precision. Servo motor control technology is constantly being developed, one of the trends is integrating real-time network into the motor controller to improve efficiency and reduce hardware costs. This paper presents the design of an AC Servo motor controller with integrated EtherCAT network. The system architecture of the EtherCAT Slave as well as the communication method between the application microcontroller and the EtherCAT Slave device are presented. Peripheral components, processing tasks of EtherCAT network-integrated motor controllers for industrial applications are analyzed in detail. Then, we propose the optimal EtherCAT controller hardware architecture both in terms of motor control and EtherCAT. The controller architecture is a combination of EtherCAT chip, high performance microcontroller and FPGA, optimized for motor control application. In addition, a prototype controller has been designed based on the proposed structure with compact size, integrated Sigma Delta ADC, USB interface, Digital I/O and support for a variety of position feedback sensors. Some important points of the CIA-402 Driver profile standard such as operating structure, state machine management, Cyclic synchronous position control mode are analyzed and applied to closed-loop control of AC servo motor. The controller is connected to the EtherCAT master and operates in a real-time environment. Test results and measurements have been checked to demonstrate the controller's operability in the EtherCAT network as well as AC Servo motor controller responsiveness.