High-performance Complementary Metal Oxide Semiconductor Research Articles

In-Depth Analysis on Self Alignment Effect of the Fermi-Level Using Graphene on Both n- and p-Type Semiconductors.

Optimizing the contact structure while reducing the contact resistance in advanced transistors has become an extremely challenging problem. Because the existing techniques are limited to controlling only one semiconductor type, either n- or p-type, owing to their work function differences, significant challenges are encountered in the integration of a contact structure and metal suitable for both n- and p-type semiconductors. This is a formidable drawback of the complementary metal-oxide-semiconductor (CMOS) technology. In this paper, we demonstrate the effectiveness of a metal/graphene/semiconductor (MGrS) as a universal source/drain contact structure for both n- and p-type transistors. The MGrS contact structure significantly enhanced the reverse current density (JR) and reduced the Schottky barrier height (SBH) for both semiconductor types. From the analysis of the SBH values and their relationship with the metal work function, which refers to the S-parameter, the van der Waals contact of graphene (Gr) effectively alleviated the Fermi level (FL) pinning for both semiconductor types, reducing the metal-induced gap states (MIGS) at the Gr/semiconductor interface. Furthermore, Gr effectively modulated the work function of the contact metal to yield a position favorable for each semiconductor type. Consequently, a single MGrS contact structure on a Si substrate resulted in excellent Ohmic contacts in both n- and p-type Si, with SBH values reduced to 0.012 and 0.024 eV for n- and p-type Si, respectively. This new approach for integrating the contact structures of semiconductor types will lead to extended capabilities for high-performance device applications and CMOS logical circuitry.

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Effect of ammonium halide salts on wet chemical nanoscale etching and polishing of InGaAs surfaces for advanced CMOS devices

Wet surface treatment of InGaAs is crucial for high-performance complementary metal-oxide semiconductor (CMOS) devices as it reduces material loss and oxide formation in the InGaAs layer. In this present study, the surface chemistries of In0.53Ga0.47As during wet chemical etching and the chemical-mechanical planarization (CMP) process in acidic (HCl/H2O2/H2O mixture) and alkaline (NH4OH/H2O2/H2O mixture) solutions were investigated. Elemental oxide formation, surface termination, and stoichiometry after the chemical etching/CMP process were investigated through X-ray photoelectron spectroscopy and atomic force microscopy. In wet chemical etching, the dissolution of the InGaAs elemental oxide was more prominent in acidic HCl mixture solutions compared to alkaline NH4OH mixture solutions. It was observed that the overall surface etching was more aggressive in acidic solution, whereas the alkaline solution provided higher surface roughness (Ra, ∼7.19 nm, scanning area of 5 μm × 5 μm) due to the lower dissolution capacity of indium oxide. The effects of the oxidizer and the slurry pH on the removal rate, Ra, and surface contamination were evaluated after the InGaAs CMP process. A high removal rate (∼110 nm/min) and considerably lower surface contamination were obtained using an alkaline slurry (pH 10). A novel InGaAs CMP slurry is developed by adding different ammonium halide salts to the alkaline slurry for improving surface roughness and removal rate. The addition of ammonium halide salts to an alkaline slurry was very effective in achieving a higher removal rate (∼175 nm/min) and smoother surface (Ra < 0.6 nm) with lower contamination during the InGaAs CMP process.

Enhanced performance of p-type SnO x thin film transistors through defect compensation

Due to the unique outermost orbitals of Sn, hole carriers in tin monoxide (SnO) possess small effective mass and high mobility among oxide semiconductors, making it a promising p-channel material for thin film field-effect transistors (TFTs). However, the Sn vacancy induced field-effect mobility deterioration and threshold voltage (V th) shift in experiments greatly limit its application in complementary metal-oxide-semiconductor (CMOS) transistors. In this study, the internal mechanism of vacancy defect compensation by aluminum (Al) doping in SnO x film is studied combining experiments with the density functional theory (DFT). The doping is achieved by an argon (Ar) plasma treatment of Al2O3 deposited onto the SnO x film, in which the Al2O3 provides both the surface passivation and Al doping source. Experimental results show a wide V th modulation range (6.08 to −19.77 V) and notable mobility enhancement (11.56 cm2V−1s−1) in the SnO x TFTs after the Al doping by Ar plasma. DFT results reveal that the most possible positions of Al in SnO and SnO2 segments are the compensation to Sn vacancy and interstitial. The compensation will create an n-type doping effect and improve the hole carrier transport by reducing the hole effective mass (m h*), which is responsible for the device performance variation, while the interstitial in the SnO2 segment can hardly affect the valence transport of the film. The defect compensation is suitable for the electronic property modulation of SnO towards the high-performance CMOS application.

Stress-Released Amorphous Oxide/Carbon Nanotube CMOS Amplifier Circuits for Skin-Compatible Electronics

Recently, there has been a great interest for realizing flexible, cheap, smart, and disposable bioelectronics and implantable electronic systems that can collect various types of in vivo biological signals from the body. In these cases, highly flexible amplifier circuits are often demanded as a basic building block for the realization of the bioelectronic systems with high signal-to-noise ratio. Here, we report highly flexible amorphous indium–gallium–zinc oxide (a-IGZO)/single-walled carbon nanotube (SWCNT) thin-film-transistor-based hybrid-type complementary metal oxide semiconductor (CMOS) amplifiers by introducing a stress-diffusive mesa-island structure. The hybrid amplifier showed stable operation under extremely stressed conditions (bending radius of 125 μm, 10000 cycles) without significant degradation, exhibiting a maximum gain of ∼21.6 dB at 0.1–5 kHz with a gain loss of −9.9 dB/dec over 10 kHz. Additionally, to ensure the viability of the developed stress-released CMOS circuits, we provided a circuit level physical modeling and synthetic analysis using structural and electrical characterizations along with multidomain finite-element analysis (FEA) and AIM-Spice simulation, verifying the acts of the materials and device architecture as a way of highly reliable and outperforming skin-compatible amplifier circuits. The results reported here imply that further neutral layer generation and its intermediate location can be controlled by device architectures and component materials, offering extremely reliable and high performance CMOS amplifier circuits for large-scaled skin-compatible on-chip applications.

Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Realization of wafer-scale single-crystalline GaN film on CMOS-compatible Si(100) substrate by ion-cutting technique

Heterogeneous integration of gallium nitride (GaN) film on complementary metal-oxide-semiconductor (CMOS)-compatible Si(100) substrate provides a material platform for future high-performance chips with multiple functions. In this work, a 2 inch wafer-scale single-crystalline GaN film is transferred from commercialized bulk GaN wafer onto Si(100) substrate by combining ion-slicing and modified surface-activated bonding with a sputtering-deposited Si nanolayer. The H+ implantation fluence for the exfoliation of GaN film is as low as 2.5 × 1017 cm−2 and the full width at half maximum of the (0002) x-ray rocking curve of GaN film is 203 arcsec. The sliced bulk GaN wafer is recycled, which is beneficial to reduce the cost and to enhance the mass application of the ion-cutting technique to GaN. The exfoliation mechanism of H-implanted GaN is investigated. The activation energy for slicing GaN is only 2.08 eV owing to the high quality of the GaN wafer, while the wide residual damage band is still an obstacle to improving the quality of the GaN film. The successful demonstration of wafer-scale single-crystalline GaN film on Si(100) substrate will be of great benefit to the integration of high-performance GaN devices and Si CMOS integrated circuits with mature processing technology.

Elemental behaviors of InGaAs surface after treatment in aqueous solutions

Indium gallium arsenide (InGaAs) is one of the candidates as a channel material for the high-performance complementary metal-oxide-semiconductor (CMOS) devices superior to silicon-based CMOS devices because of its higher electron mobility. In order to introduce InGaAs as a new channel material for high-performance CMOS devices, it is important to prepare its surface to suppress material loss and surface oxide formation in the InGaAs layer. In this study, the behavior of each element of the In0.53Ga0.47As surface in chemical solutions such as HCl, NH4OH, HPM (HCl/H2O2/H2O) and APM (NH4OH/H2O2/H2O) was investigated from the viewpoint of thermodynamics and reaction kinetics. In the acidic HCl solution, the dissolution of the InGaAs surface was the dominant reaction, whereas a sub-oxide formed on the InGaAs surface in the basic NH4OH solution. The formation of the oxide on the surface was considered the rate-limiting step of the overall etching reaction of InGaAs in the acidic solution; therefore, the surface oxidation and overall etching (dissolution) of the InGaAs layer were determined using different amounts of H2O2 in the solution. In particular, the overall etching of the InGaAs surface in the HPM solution was more aggressive than that in the APM solution. The behavior of InGaAs in the surface preparation process sequences with APM, HPM, and HF was also investigated, and it was observed that the material loss and surface roughening of the InGaAs layer were mostly determined in the HPM process. Finally, it was possible to suppress the surface oxidation, material loss, and surface roughening of the InGaAs layer by reducing the concentration of H2O2 in the HPM solution.

Ultralow Defect Density at Sub-0.5 nm HfO2/SiGe Interfaces via Selective Oxygen Scavenging.

The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high- k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeO x. This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeO x at the interface; the remaining ultrathin interlayer is consistent with a SiO x-rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiO x-rich surface layer can produce an electrically passivated HfO2/SiGe interface. To form this SiO x-rich interlayer, metal gate stack designs including Al/HfO2/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO2-Al2O3) were investigated. As compared to the control Ni-gated devices, those with Al/HfO2/SiGe gate stacks demonstrated more than an order of magnitude reduction in interface defect density with a sub-0.5 nm SiO x-rich interfacial layer. To further increase the oxide capacitance, the devices were fabricated with a Ti oxygen scavenging layer separated from the HfO2 by a conductive TiN diffusion barrier (remote scavenging). The Pd/Ti/TiN/NL/SiGe structures exhibited significant capacitance enhancement along with a reduction in interface defect density.

Ultra-Fast Switching of a Free Magnetic Layer with out-of-Plane Magnetization in Spin-Orbit Torque Mram Cells

Continuous miniaturization of complementary metal-oxide semiconductor (CMOS) devices is one of the driving forces for the unprecedented increase of speed and performance delivered by modern integrated circuits However, a rapid increase of the stand-by power due to transistor leakages and the need to refresh the data in dynamic random access memory (DRAM) is becoming a pressing issue. The microelectronics industry is facing major challenges related to power dissipation and energy consumption, and the microprocessors’ scaling will hit a power wall soon. An attractive path to mitigate the unfavorable trend of increasing power at stand-by is to introduce non-volatility in the circuits. The development of an electrically addressable non-volatile memory which combines fast operation, simple structure, and high endurance is essential to mitigate the increase of the stand-by power and to introduce instant-on architectures without the need of data initialization when going from a stand-by to an operation regime. Oxide-based resistive RAM (RRAM) possesses filamentary switching between on/off states and is thus intrinsically prone to significant resistance fluctuations in both on and off states. In addition, the endurance reported is only slightly higher than that in flash memory. For this reason, it is premature to consider RRAM at its current stage of development for digital applications. Since continuous conductance modulation is suitable for implementing analog synaptic weights, both filamentary and non-filamentary switching RRAM types are currently intensively investigated, particularly also for neuromorphic applications [1]. Spin-transfer torque magnetic RAM (STT-MRAM) is fast (10ns), possesses high endurance (1012), and a simple structure. It is compatible with CMOS and can be straightforwardly embedded in circuits, e.g. [2]. High-density STT-MRAM arrays with 4Gbit capacities have been already demonstrated [3]. The availability of high-capacity non-volatile memory positioned close to high-performance CMOS circuits opens a new horizon in exploring conceptually new logic-in-memory [4] and computing-in-memory architectures for future artificial intelligence and cognitive computing. Although it might be possible to introduce STT-MRAM in L3 caches, the memory is too slow for entering L1 and L2 caches currently mastered by static RAM (SRAM). In addition, rapidly increasing critical currents for switching STT-MRAM at 5ns and faster reduce the endurance to that of the flash memory. The development of an electrically addressable non-volatile memory combining high speed (sub-ns operation) and high endurance is essential for replacing SRAM) in high-level caches of hierarchical multi-level processor memory structures with a non-volatile memory [4]. The spin-orbit torque MRAM (SOT-MRAM) with perpendicular magnetization combines non-volatility, high speed, and high endurance, which makes it suitable for applications in caches [5]. However, its development is still hindered by the need of an external magnetic field to guarantee deterministic switching [6]. We apply the two-pulse scheme previously proposed for switching of an in-plane structure [7]. The SOT due to the first 100ps pulse tilts the magnetization of the free layer in-plane perpendicular to the direction of the “Write pulse 1” (Fig.1). The SOT of the second consecutive pulse results in an additional precession of the magnetization in the part of the free layer under it, which is transferred to the remaining part of the free layer through the exchange interaction. Depending on the spin of this precession, the magnetization of the remaining part tilts up or down with respect to the in-plane orientation. The part under the wire of “Write pulse 2” follows the precession after the current is turned off, thus completing the switching. Results of the switching time calculations for several pulse durations as a function of the width of the second pulse wire are shown in Fig.2. We conclude that the fastest, sub-300ps switching, is achieved at around 30% overlap of the second pulse wire with the free layer. REFERENCES G.W. Burr, R.M. Shelby, A.Sebastian et al., “Neuromorphic Computing Using Non-volatile Memory”, Advances in Physics:X 2, 89 (2017).D.Apalkov, B.Dieny, J.M. Slaughter, “Magnetoresistive Random Access Memory”, Proceedings of the IEEE 104, 1796 (2016).S.-W. Chung, T.Kishi, J. W. Park et al.,“ 4Gbit Density STT-MRAM Using Perpendicular MTJ Realized with Compact Cell Structure”, IEDM 2016 Techn. Digest, 660.T.Hanyu, T.Endoh, D.Suzuki, H.Koike, et al. “Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing”, Proceedings IEEE 104, 1844 (2016).S.-W. Lee and K.-J. Lee, “Emerging Three-Terminal Magnetic Memory Devices”, Proceedings IEEE 104, 1831 (2016).S.Fukami, T.Anekawa, C.Zhan, et al. “A Spin–orbit Torque Switching Scheme with Collinear Magnetic Easy Axis and Current Configuration“, Nature Nanotechnology 11, 621 (2016)A.Makarov, T.Windbacher, V.Sverdlov, and S.Selberherr, “CMOS-compatible Spintronic Devices: A Review” Semiconductor Science and Technology 31, 113006 (2016). Figure 1

High-Performance Carbon Nanotube Complementary Electronics and Integrated Sensor Systems on Ultrathin Plastic Foil.

The longtime vacancy of high-performance complementary metal-oxide-semiconductor (CMOS) technology on plastics is a non-negligible obstacle to the applications of flexible electronics with advanced functions, such as continuous health monitoring with in situ signal processing and wireless communication capabilities, in which high speed, low power consumption, and complex functionality are desired for integrated circuits (ICs). Here, we report the implementation of carbon nanotube (CNT)-based high-performance CMOS technology and its application for signal processing in an integrated sensor system for human body monitoring on ultrathin plastic foil with a thickness of 2.5 μm. The performances of both the p- and n-type CNT field-effect transistors (FETs) are excellent and symmetric on plastic foil with a low operation voltage of 2 V: width-normalized transconductances ( gm/ W) as high as 4.69 μS/μm and 5.45 μS/μm, width-normalized on-state currents reaching 5.85 μA/μm and 6.05 μA/μm, and mobilities up to 80.26 cm2·V-1·s-1 and 97.09 cm2·V-1·s-1, respectively, together with a current on/off ratio of approximately 105. The devices were mechanically robust, withstanding a curvature radius down to 124 μm. Utilizing these transistors, various high-performance CMOS digital ICs with rail-to-rail output and a ring oscillator on plastics with an oscillation frequency of 5 MHz were demonstrated. Furthermore, an ultrathin skin-mounted humidity sensor system with in situ frequency modulation signal processing capability was realized to monitor human body sweating.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm2 V-1 s-1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V.

Trapping and diffusion behaviour of hydrogen simulated with TCAD in projection range of carbon‐cluster implanted silicon epitaxial wafers for CMOS image sensors

The trapping and diffusion behaviour of hydrogen in projection range of carbon‐cluster was investigated by using a technology computer aided design (TCAD) simulation for high performance complementary metal–oxide–semiconductor (CMOS) image sensors. The hydrogen behaviour seemingly contributes to passivating the interface state density of the isolation region and process‐induced defects during the CMOS image sensor fabrication process. This hydrogen behaviour was simulated by a TCAD simulation assuming a reaction model in which the cluster of carbon and silicon self‐interstitial (carbon‐interstitial cluster) binds to hydrogen. We found that the hydrogen profiles of TCAD agreed with the secondary ion mass spectrometry (SIMS) results after epitaxial growth and high‐temperature heat‐treatment, thus suggesting that the hydrogen in the projection range of the carbon cluster forms a binding state with the carbon‐interstitial cluster. In addition, hydrogen gradually diffused out from the projection range of the carbon‐cluster after high‐temperature heat‐treatment. Therefore, the hydrogen behaviour in projection range of the carbon‐cluster is considered to contribute to the CMOS image sensor fabrication process to achieve high electrical performance.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Printed Organic and Inorganic Electronics: Devices To Systems

Affordable and versatile printed electronics can play a critical role for large area applications, such as for displays, sensors, energy harvesting, and storage. Significant advances including commercialization in the general area of printed electronics have been based on organic molecular electronics. Still some fundamental challenges remain: thermal instability, modest charge transport characteristics, and limited lithographic resolution. In the last decade, one-dimensional nanotubes and nanowires, like carbon nanotubes and silicon nanowires, followed by two-dimensional materials, like graphene and transitional dichalcogenide materials, have shown interesting promise as next-generation printed electronic materials. Challenges, such as non-uniformity in growth, limited scalability, and integration issues, need to be resolved for the viable application of these materials to technology. Recently, the concept of printed high-performance complementary metal–oxide semiconductor electronics has also emerged and been proven successful for application to electronics. Here, we review progress in CMOS technology and applications, including challenges faced and opportunities revealed.

Decal Electronics: Printable Packaged with 3D Printing High‐Performance Flexible CMOS Electronic Systems

High-performance complementary metal oxide semiconductor electronics are flexed, packaged using 3D printing as decal electronics, and then printed in roll-to-roll fashion for highly manufacturable printed flexible high-performance electronic systems. As a service to our authors and readers, this journal provides supporting information supplied by the authors. Such materials are peer reviewed and may be re-organized for online delivery, but are not copy-edited or typeset. Technical support issues arising from supporting information (other than missing files) should be addressed to the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

(Invited) Anisotropic Strain Introduction into Si/Ge Hetero Structures

Ge is one of the most attractive materials toward ultra-low-power and high-performance complementary metal oxide semiconductor (CMOS) circuits owing to its higher hole mobility than Si and various III-V materials. Moreover, it is possible to enhance the mobility further by introducing strain into the channel. Especially an uniaxial strain is expected to provide the highest hole mobility [1,2]. So far, several approaches have been researched to create uniaxially strained SiGe and Ge channels. We have been developing the selective ion implantation technique to induce uniaxial strain into SiGe buffer layers [3,4]. In this method, a Si substrate is selectively subjected to the ion implantation and followed by the SiGe overgrowth. A subsequent post-growth-annealing promotes the strain relaxation of the SiGe selectively in the implanted region as the implantation-induced defects formed act as dislocation nucleation sources. And hence, with proper configurations of the selective implantation, the anisotropic strain can be induced in the SiGe in the unimplanted area since the neighboring relaxed SiGe films in the ion-implanted areas provide shear stress at the interfaces. In previous works, we succeeded in fabrication of uniaxially strained SiGe buffer layers with Ge concentrations below 30% [3,4], which can serve as proper templates for uniaxially strained Si/Ge heterostructures, such as uniaxially strained Si and Si1-xGex (x < 0.5) channels. For the formation of uniaxially strained Ge and Si1-xGex(x > 0.5) channels, however, SiGe buffers with higher Ge concentrations are required. In this study, therefore, we fabricate uniaxially strained SiGe buffer layers with high Ge concentrations with the selective ion implantation technique and overgrew uniaxially strained Ge layers on the SiGe buffers. The sample fabrication procedure is as follows (Fig.1). Ar+ ions were selectively implanted into the Ge substrate through the SiO2 mask window. Line widths of the ion-implanted and unimplanted regions were varied from 2 to 20 μm. A SiGe layer was pseudomorphically grown on the selectively ion-implanted Ge substrate with solid source molecular beam epitaxy. Subsequently, postgrowth annealing was carried out to promote the strain relaxation of the SiGe only in the implanted region. Finally a Ge layer with the thickness of 10 nm was pseudomorphically grown on the SiGe. Figure 2 shows a Raman mapping image for the sample with 3-μm-width stripe lines, where a Ge-Ge mode peak wavenumbers obtained from the top Ge layer were scanned. A clear contrast is observed corresponding to the large and small compressive strain of the Ge layer in the implanted and unimplanted regions, respectively. This demonstrates that the strain of the Ge is laterally controlled by the selective implantation. Since XRD measurements confirmed that the SiGe buffer layer has uniaxial strain, it can be said that the top Ge layer is also uniaxially strained. This uniaxially strained Ge layer can be transferred onto the insulator substrate via wafer bonding process, where the ion-implanted defective region can be removed. Finally defect-free uniaxially strained GOI substrate can be obtained, which is applicable to high mobility uniaxilly strained Ge channel MOSFETs. [1] Y. Sun, et al., J. Appl. Phys. 101, 104503 (2007). [2] T. Krishnamohan et al., IEDM Tech. Dig., 899 (2008). [3] K. Sawano et al., Appl.Phys.Express 1, 121401 (2008). [4] K. Sawano et al., J. of Crystal Growth 378, 251 (2013). Figure 1

Low-voltage operation of ZrO2-gated n-type thin-film transistors based on a channel formed by hybrid phases of SnO and SnO2.

With SnO typically regarded as a p-type oxide semiconductor, an oxide semiconductor formed by hybrid phases of mainly SnO and a small amount of SnO2 with an average [O]/[Sn] ratio of 1.1 was investigated as a channel material for n-type thin-film transistors (TFTs). Furthermore, an appropriate number of oxygen vacancies were introduced into the oxide during annealing at 400 °C in ambient N2, making both SnO and SnO2 favorable for current conduction. By using high-κ ZrO2 with a capacitance equivalent thickness of 13.5 nm as the gate dielectric, the TFTs processed at 400 °C demonstrated a steep subthreshold swing (SS) of 0.21 V/dec, and this can be ascribed to the large gate capacitance along with a low interface trap density (Dit) value of 5.16 × 10(11) cm(-2) eV(-1). In addition, the TFTs exhibit a relatively high electron mobility of 7.84 cm(2)/V·s, high ON/OFF current ratios of up to 2.5 × 10(5), and a low gate leakage current at a low operation voltage of 3 V. The TFTs also prove its high reliability performance by showing negligible degradation of SS and threshold voltage (VT) against high field stress (-10 MV/cm). When 3% oxygen annealing is combined with a thinner channel thickness, TFTs with even higher ION/IOFF ratios exceeding 10(7) can also be obtained. With these promising characteristics, the overall performance of the TFTs displays competitive advantages compared with other n-type TFTs formed on binary or even some multicomponent oxide semiconductors and paves a promising and economic avenue to implement an n-type oxide semiconductor without doping for production-worthy TFT technology. Most importantly, when combined with the typical SnO-based p-type oxide semiconductor, it would usher in a new era in achieving high-performance complementary metal oxide semiconductor circuits by using the same SnO-based oxide semiconductor.

A novel ±0.8 V high-performance voltage-tunable CDTA with enhanced bandwidth

In this article, we propose a novel high-performance complementary metal oxide semiconductor (CMOS) current differencing transconductance amplifier (CDTA) with a transconductance gain (GM) that can be linearly tuned by a voltage. By using a high-speed, low-voltage, cascaded current mirror active resistance compensation technique, the proposed CDTA circuit exhibits wide frequency bandwidths, high current tracking precisions as well as large output impedances. The linear-tunable GM of the CDTA is designed with the use of linear composite metal oxide semiconductor field-effect transistor as basic cells in the circuit. Combining these two approaches, several design concerns are studied, including: impedance characteristic, tracking errors, offset and linearity and noise. The prototype chip with a 0.25 mm2 area is fabricated in a GlobalFoundries’0.18 μm CMOS process. The simulated results and measured results with ±0.8 V DC supply voltages are presented, and show extremely wide bandwidths and wide linear tuning range. In addition, a fully differential band-pass filter for a high-speed system is also given as an example to confirm the high performance of the proposed circuit.

Flexible nano-hybrid inverter based on inkjet-printed organic and 2D multilayer MoS2 thin film transistor

We report a novel platform on which we design a flexible high-performance complementary metal–oxide–semiconductor (CMOS) inverter based on an inkjet-printed polymer PMOS and a two-dimensional (2D) multilayer molybdenum disulfide (MoS2) NMOS on a flexible substrate. The initial implementation of a hybrid complementary inverter, comprised of 2D MoS2 NMOS and polymer PMOS on a flexible substrate, demonstrates a compelling new pathway to practical logic gates for digital circuits, achieving extremely low power consumption with low sub-1nA leakage currents, high performance with a voltage gain of 35 at 12V supply voltage, and high noise margin (larger than 3V at 12V supply voltage) with low processing costs. These results suggest that inkjet-printed organic thin film transistors and 2D multilayer semiconducting transistors may form the basis for potential future high performance and large area flexible integrated circuitry applications.