High-performance ADCs Research Articles

Discovery and Engineering of a Novel Bacterial L-Aspartate α-Decarboxylase for Efficient Bioconversion.

L-aspartate α-decarboxylase (ADC) is a pyruvoyl-dependent decarboxylase that catalyzes the conversion of L-aspartate to β-alanine in the pantothenate pathway. The enzyme has been extensively used in the biosynthesis of β-alanine and D-pantothenic acid. However, the broad application of ADCs is hindered by low specific activity. To address this issue, we explored 412 sequences and discovered a novel ADC from Corynebacterium jeikeium (CjADC). CjADC exhibited specific activity of 10.7 U/mg and Km of 3.6 mM, which were better than the commonly used ADC from Bacillus subtilis. CjADC was then engineered leveraging structure-guided evolution and generated a mutant, C26V/I88M/Y90F/R3V. The specific activity of the mutant is 28.8 U/mg, which is the highest among the unknown ADCs. Furthermore, the mutant displayed lower Km than the wild-type enzyme. Moreover, we revealed that the introduced mutations increased the structural stability of the mutant by promoting the frequency of hydrogen-bond formation and creating a more hydrophobic region around the active center, thereby facilitating the binding of L-aspartate to the active center and stabilizing the substrate orientation. Finally, the whole-cell bioconversion showed that C26V/I88M/Y90F/R3V completely transformed 1-molar L-aspartate in 12 h and produced 88.6 g/L β-alanine. Our study not only identified a high-performance ADC but also established a research framework for rapidly screening novel enzymes using a protein database.

Design of High Performance and Power Efficient Flash ADC

In this paper, Flash Analog to digital converter is implemented. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using Tanner tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Here, we are modifying the structure of operational Amplifier using Power Gating Technique. Binary code is obtained from the thermometer code by utilizing a Mux based encoder by designing the MUX in domino Logic. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the propagation delay of the ADC by optimizing encoder circuitry. With the purpose of reducing latency, Encoder is implemented using 2:1 mux based on Pseudo NMOS Logic. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.

High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers

High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers

ВИСОКОЛІНІЙНІ БУФЕРИ НАПРУГИ ДЛЯ ВИСОКОПРОДУКТИВНИХ АЦП І ЦАП

The article analyzes the proposed methods of structural and functional organization of highly linear voltage buffers built according to two-stroke symmetrical structures. In the first method, it is assumed to increase the resistance of the current outputs. Thanks to this, it is possible to stabilize the collector-emitter junction voltage of the transistors of the output stages. In the second method, it is proposed to reduce the influence of the base current of the transistors of the output stages, which will reduce the linearity error. In the third method, it is proposed to increase the linearity without reducing the speed level, by stabilizing the collector-emitter voltages of the output stages. It is shown that the use of voltage stabilization of the collector-emitter transitions makes it possible to improve the circuit characteristics by 1÷2 orders of magnitude. Analytical dependencies describing the linearity errors of the cores of voltage buffers, which are built according to a two-stroke symmetrical structure, are derived. It is shown that the proposed approaches allow to reduce the errors of linearity and zero shift by an order of magnitude or more. To determine the components that affect the appearance of the error, an equivalent scheme for replacing the output of the voltage buffer core is considered. It was determined that the proposed methods of building voltage buffers have a common drawback, namely, low load capacity, which is determined by the output resistances of the circuits. An approach that allows increasing the load capacity of voltage buffers is considered. It is shown that it makes it possible to reduce the output resistance by 2÷3 orders of magnitude. In order to increase the load capacity and maintain the specified linearity of the voltage buffer scheme, it is proposed to supplement it with a two-stroke two-channel current amplifier. The use of the proposed methods and approaches for the construction of voltage buffers allows obtaining such devices that have the necessary characteristics and can be used as part of high-performance ADCs and DACs.

Design of a Sampler circuit for Flash ADC using 45nm Technology

This paper presents design of a sampler circuit for folding flash ADC. There is a desire for Low power high performance ADC for communication. For low power the size of the ADC should be minimized and for the fast performance flash can be used. Hence to reduce the number of transistors in flash ADC folding network is proposed here. Sampling is the important technique used in the ADC part. In this discussion the sampler circuit includes a differential track and hold switch followed by a variable gain amplifier with a gain of 1 db, a buffer and a folding network. An input voltage of1 V and the sampling frequency of 1GS/s is applied to the sampler circuit. Effective number of bits of more than 5.7 bits is achieved also THD is below -35db in VGA. Buffer achieves a ENOB of 10bits with THD less than -65db. This sampler circuit is designed with the technology of 45nm for coherent sampling. Worst case SNDR is calculated.

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 µm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.

A 9 b/12 b 50 MS/s experimental ADC with continuous approximation architecture in 65 nm CMOS

A 9 bits 50 MS/s 0.5 mW continuous approximation mixed successive approximation (CAR&SAR) ADC is presented. A 12 bits 50 MS/s 0.6 mW CAR&CAR ADC is presented. In the field of low power and high performance ADC, CAR is a new architecture different from SAR. It is faster and easier to get high accuracy. Here we will introduce CAR and its circuit implementation, and the 9 bits experimental ADC is designed to verify CARADC's feasibility. Meanwhile, its resolution can be extended to 12 bits with adding an extra CAR, and then the performance is raised to 0.6 mW 50 MS/s 72 dB SNDR at TT corner and the Walden FOM is 3.6 fj/conv-step. The 9 b ADC was fabricated by using TSMC 1P9M 65 nm CMOS technology. The ADC achieves 50 dB SNDR and the realized Walden FOM is 34 fj/conv-step. The simulation and measurement results prove that CAR is available in the low power and high performance ADC and it even outperforms SAR. The ADC core occupies an active area of 0.045 mm2.

Characterization of MEMS resonators via feedthrough de-embedding of harmonic and subharmonic pulsed-mode response

In this paper, we model and give experimental evidence of the efficiency of pulsed-mode actuation for the characterization of capacitive MEMS resonators. In particular, we show how to process the pulsed-mode response in two modes (harmonic and subharmonic) so as to eliminate parasitic feedthrough effects and characterize the resonator more accurately. We test our approach on a pressure sensor, developed by THALES Avionics, used for avionics applications. In contrast to the existing state-of-the-art techniques, the methods described in this paper can be used to characterize electrostatic MEMS without the use of a spectrum analyzer or high-performance ADC.

Characterization of MEMS Resonators via Feedthrough De-embedding of Pulsed-mode Response

In this paper, we analyze and give experimental evidence of the efficiency of pulsed-mode actuation for the characterization of capacitive MEMS resonators. In particular, we show how to process the output signal in pulsed mode to eliminate parasitic feedthrough effects and characterize the resonator. We test our approach on a pressure sensor, developed by THALES Avionics, used for avionics applications. Contrary to the existing state-of-the-art techniques, the method described in this paper can be used to characterize an electrostatic MEMS without a spectrum analyzer or high-performance ADC.

Design of a High Precision, Wide Ranged Analog Clock Generator with Field Programmability Using Floating-Gate Transistors

This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.

ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator

Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.

The DSP bottleneck

The stumbling blocks in development of a commercially usable software radio have been the availability of hardware, in particular the fast DSP required. As high performance ADCs have become available commercially, with the sample rates and spurious free dynamic ranges required, hybrid techniques using specialized digital hardware, operating under software control, have become more common. >