High-level Processor Research Articles

The Neural Correlates of Access Consciousness and Phenomenal Consciousness Seem to Coincide and Would Correspond to a Memory Center, an Activation Center and Eight Parallel Convergence Centers.

An increasing number of authors suggest that the neural correlates of consciousness (NCC) have no selective, executive, or metacognitive function. It is believed that attention unconsciously selects the contents that will become conscious. Consciousness would have only the fundamental function of transforming the selected contents into a format easily used by high-level processors, such as working memory, language, or autobiographical memory. According to Dehaene, the neural correlates (NC) of access consciousness (AC; cognitive consciousness) constitute a widespread network in the frontal, parietal, and temporal cortices. While Tononi localized the correlates of phenomenal consciousness (PC; subjective consciousness) to a posterior “hot zone” in the temporo-parietal cortex. A careful examination of the works of these two groups leads to the conclusion that the correlates of access and PC coincide. The two consciousnesses are therefore two faces of the same single consciousness with both its cognitive and subjective contents. A review of the literature of the pathology called “neglect” confirms that the common correlates include 10: a memory center, an activation center, and eight parallel centers. From study of the “imagery” it can be deduced that these eight parallel centers would operate as points of convergence in the third person linking the respective eight sensory-motor-emotional areas activated by external perceptions and the corresponding memories of these perceptions deposited in the memory center. The first four centers of convergence appear in the most evolved fish and gradually reach eight in humans.

Cloud based analysis of Drinking Water quality parameters

The contamination of water bodies becomes a very big threat to the world. This happens due to pollution, domestic and industry waste and over population. This threat will lead to low rainfall, famines etc. In recent years, the research on monitoring and analyzing water quality is increasing. The water quality has to be examined in people living area, ponds, lakes, rivers and also the water bodies near the industries. People not having safe drinking water will lead to many diseases. The older methods of officials collecting sample from the water bodies, analyzing in labs, providing the results and taking control actions will be costly and takes more time. The main disadvantage is the lack of real time data analysis is not possible in the traditional systems. In this paper, a real time water quality method is analyzed and the results are verified with the traditional methods. This method uses high level processor, sensors, networking and measurement devices to give the real time data. The important parameters of water like temperature, turbidity and pH levels are monitored continuously. The user can verify the data anywhere anytime using the web interface provided in the method. The data analysis is also provided in tabulation and graphical representations. This paper provides an optimal method for monitoring the water quality in an efficient way. Traditional methods that rely on collecting water samples, testing and analyses in water laboratories are not only costly but also lack the capability for real-time data capture, analyses and fast dissemination of information to relevant stakeholders for making timely and informed decisions.

Survey on automated symbolic verification and its application for synthesising cyber‐physical systems

Dependency on the correct operation of embedded systems is rapidly growing, mainly due to their wide range of applications. Their structures are becoming more complex and currently require multi-core processors with scalable shared memory, signal-processing pipelines, and sophisticated software modules to meet increasing computational power, flexibility demands. Additionally, interaction with real-world entities and modern communication capabilities further enhance the mentioned features and give rise to the embedded and cyber-physical systems (ECPS). As a consequence, the reliability of ECPS becomes a key issue during system development. Generally, state-of-the-art verification methodologies for ECPS generate test vectors and use assertion-based verification and high-level processor models, during simulation; however, new challenges arose, such as need for meeting time and energy constraints, handling concurrent software, evaluating implementation-structure choices, ensuring correct system behavior together with physical plants, and supporting new software architectures and legacy designs. This survey deals with the mentioned issues, reviews related literature, and discusses recent advances in symbolic model checking techniques and their applications to control synthesis. Additionally, challenges, problems, and recent advances to ensure correctness and timeliness, regarding ECPS, are discussed. Reliability issues, when developing ECPS, are then considered, as a prominent verification and synthesis application for achieving correct-by-construction systems.

Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

SMT-Based Context-Bounded Model Checking for Embedded Systems

The dependency on the correct functioning of embedded systems is rapidly growing, mainly due to their wide range of applications, such as micro-grids, automotive device control (e.g., airbag control), health care, surveillance, mobile devices, and consumer electronics. Their structures are becoming more and more complex and now require multi-core processors with scalable shared memory, in order to meet increasing computational power demands. As a consequence, reliability of embedded (distributed) software becomes a key issue during system development, which must be carefully addressed and assured. Normally, state-of-the-art verification methodologies for embedded systems generate test vectors (with constraints) and use assertion-based verification and highlevel processor models, during simulation; however, other additional challenges have been raised: the need for meeting time and energy constraints, handling concurrent software, dealing with platform restrictions, evaluating implementation-structure choices, and supporting new software architectures and legacy designs (usually written in low-level languages). The present paper discusses challenges, problems, and recent advances to ensure correctness and timeliness regarding embedded systems. Reliability issues, in the development of micro-grids and cyber-physical systems, are then considered, as a prominent (bounded) model checking application.

Cognitive Radar Framework for Target Detection and Tracking

Most radar systems employ a feed-forward processing chain in which they first perform some low-level processing of received sensor data to obtain target detections and then pass the processed data on to some higher-level processor such as a tracker, which extracts information to achieve a system objective. System performance can be improved using adaptation between the information extracted from the sensor/processor and the design and transmission of subsequent illuminating waveforms. As such, cognitive radar systems offer much promise. In this paper, we develop a general cognitive radar framework for a radar system engaged in target tracking. The model includes the higher-level tracking processor and specifies the feedback mechanism and optimization criterion used to obtain the next set of sensor data. Both target detection (track initiation/termination) and tracking (state estimation) are addressed. By separating the general principles from the specific application and implementation details, our formulation provides a flexible framework applicable to the general tracking problem. We demonstrate how the general framework may be specialized for a particular problem using a distributed sensor model in which system resources (observation time on each sensor) are allocated to optimize tracking performance. The cognitive radar system is shown to offer significant performance gains over a standard feed-forward system.

Nanosensor Data Processor in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates, and (iii) generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.

Teaching Robotics Software With the Open Hardware Mobile Manipulator

The open hardware mobile manipulator (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and software source codes are available under free licenses enabling the community to adapt and update the design as the field (and available hardware) evolves. Digital manufacturing (3-D printing and laser cutting) methods, now available as low-cost Internet services, enable OHMM to be easily modified and to be built from scratch for a competitive price. Five hands-on curriculum modules are presented that use OHMM to teach robotics software and algorithms at the undergraduate and graduate levels, and results are presented based on student performance and feedback.

Energy-performance tradeoffs in processor architecture and circuit design

Power consumption has become a major constraint in the design of processors today. To optimize a processor for energy-efficiency requires an examination of energy-performance trade-offs in all aspects of the processor design space, including both architectural and circuit design choices. In this paper, we apply an integrated architecture-circuit optimization framework to map out energy-performance trade-offs of several different high-level processor architectures. We show how the joint architecture-circuit space provides a trade-off range of approximately 6.5x in performance for 4x energy, and we identify the optimal architectures for different design objectives. We then show that many of the designs in this space come at very high marginal costs. Our results show that, for a large range of design objectives, voltage scaling is effective in efficiently trading off performance and energy, and that the choice of optimal architecture and circuits does not change much during voltage scaling. Finally, we show that with only two designs--a dual-issue in-order design and a dual-issue out-of-order design, both properly optimized-a large part of the energy-performance trade-off space can be covered within 3% of the optimal energy-efficiency.

RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions

Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. In this paper, we present an algorithm to automatically generate RTs from a high-level processor description with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turnaround time in design space exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 very long instruction word digital signal processor and DLX processor architectures, and a suite of multimedia and scientific applications.

Observation of double phi-meson production in 400-GeV/c proton-nucleon interactions.

The production of phi-meson pairs has been observed in 400-GeV/c proton-nucleon interactions at the Fermilab multiparticle spectrometer in the inclusive reaction pN..-->..phiphi+X, where each phi decays to a K/sup +/K/sup -/ pair. A fast (200 nsec)= high-level processor was used to selectively trigger on events containing two pairs of oppositely charged kaons having low invariant masses. The experimental apparatus and trigger processor are described. The cross section for phiphi production and an upper limit for eta/sub c/ production are presented.

Electronic exchange system. Part 1: Structure

Continuing from another paper, the equipment for the structure of an electronic telephone exchange is described together with the reasons for the choices made. Analogue circuits are switched by p.a.m./t.d.m. (pulse-amplitude-modulation/time-division-multiplex) switches and p.c.m. (pulse-code-modulation) circuits by t.d.m. switches of the same kind. The use of t.d.m. switches profoundly influences the choice of processors for supervisory, signalling and other low-level functions, which, in turn, have some effect on the high-level common and unique common processors which are the subject of Pt. 2 of the paper.