High-level Data Link Control Research Articles

Multi-COBS: A Novel Algorithm for Byte Stuffing at High Throughput

Framing methods are used to break a data stream into packets in most digital communications. The use of a reserved symbol to denote the frame boundaries is a popular practice. This end-of-frame (EOF) marker should be removed from the packet content in a reversible manner. Many strategies, such as the bit and byte stuffing processes employed by high-level data link control (HDLC) and Point-to-Point Protocol (PPP), or the Consistent Overhead Byte Stuffing (COBS), have been devised to perform this goal. These bit and byte stuffing algorithms remove the reserved EOF marker from the packet payload and replace it with some extra information that can be used to undo the action later. The amount of data added is called <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">overhead</i> and is a figure-of-merit of such algorithms, together with the encoding and decoding speed. Multi-COBS, a new byte stuffing algorithm, is presented in this paper. Multi-COBS provides concurrent encoding and decoding, resulting in a performance improvement of factor four or eight in common word-based digital architectures while delivering an average and worst-case overhead equivalent to the state-of-the-art. On the reference 28-nanometer field programmable gate array (FPGA) (Artix-7), Multi-COBS achieves a throughput of 6.6 Gbps, instead of 1.7 Gbps of COBS. Thanks to its parallel elaboration capability, Multi-COBS is ideal for digital systems built in programmable logic as well as modern computers.

A TestBed for Deployment of Datacenter Switches for Training Purposes

Today’s network industry needs highly qualified engineers to understand, configure, develop and upgrade switches that can build scalable high performance and ultra-low latency networks. This paper describes a new networking laboratory that has been set up to provide hands-on experience on datacenter network switches, such as ARISTA, programming and monitoring the traffic. This paper explains the networking laboratory coursework that students carry out during the course of a semester. The laboratory consists of six hands on experiments on the latest datacenter switches from Arista Networks, two programming assignments that teaches some of the protocols used at data link layer and routing protocols used at the network layer of OSI reference model. The final two laboratory experiments use the Wireshark software tool for traffic monitoring and peeking into details of some of the protocols in TCP/IP such as ARP protocol, Ethernet and so forth. The coursework details include the switch basics, switch hardware, Extensible Operating System (EOS), configuration of Link Aggregation Control Protocol, Multi-chassis Link Aggregation Protocol, Access Control Lists, and Open Short Path First version 2 on Arista switches 7050T-64 and 7048T-4S. The programming tasks cover High-level Data Link Control (HDLC) and Routing Algorithms.

Wireless HDLC Protocol for Energy-Efficient Large-Scale Linear Wireless Sensor Networks

Wireless sensor networks (WSNs) have been widely recognized as a promising technology that can enhance various aspects of infrastructure monitoring. Typical applications, such as sensors embedded in the outer surface of a pipeline or mounted along the supporting structure of a bridge, feature a large-scale linear sensor arrangement. In this paper, we propose a new bidirectional wireless communication scheme, based on the high-level data link control (HDLC) standard, for devices with short-range transmission capabilities for linear sensor topology. By applying for the first time a standard data layer along with a time division multiple access (TDMA)-based medium access control (MAC) and time synchronization technique specifically designed for the linear topology, we address the interoperability problem with guaranteed energy efficiency and data link performance in linear sensor topology. The proposed Wireless HDLC supports half-duplex communication, point to point (peer to peer), and multipoint networking.

System Level Modeling of a Digital Communication Channel Based on SystemC

In order to evaluate and investigate performance of a digital communication system, this paper presents a new approach that can be used to design, model and develop a Stochastic digital channel simulator to plug into any digital communication system under different modulation schemes. The data packet structure that has been used with this system is based on a High-Level Data Link Control (HDLC) standard. The simulation tool is a SystemC that is provide various features to perform system level modeling and simulation. The challenge was how to efficiently simulate this channel by using the hardware modeling features available in SystemC, and then how we have developed this channel. Also discussed how the modeling features can be used to simulate different noise sources that can be used to introduce noise events depends on specific distribution.

Securing Authentication of TCP/IP Layer Two By Modifying Challenge-Handshake Authentication Protocol

Computer communications have been playing a vital role in the world economy. Government organizations, large companies and banks are using those networks in trading their data. This imposed a challenge due to the increasing need for protecting the sensitive data traded over those networks. This research presents a mechanism to protect computers communication over open un-trusted networks, primarily, that mechanism relies on securing communication authentication. In order to do that, the communication protection mechanism modifies the Challenge-Handshake Authentication Protocol (CHAP ) which is responsible for the authentication of communication of layer two High-level Data Link Control (HDLC ) protocol.

Composition Rule of Character Codes to efficiently transmit the Character Code in HDLC(High-level Data Link Control) Protocol

This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of 01111110. When data bit stream consist of the consecutive 5-bit 1 after 0, the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits 1 after 0 in the input data stream, inserts violently the 0 after 5th 1 of the consecutive 5-bit 1 after 0. As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits 1 after 0 when the code is given to each characters.

Design and Implementation of a Multi-Channel HDLC Protocol Controller Based on FPGA

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.

Backplane Serial Signaling and Protocol for Telecom Systems

In this paper, we implement a modern serial backplane platform for telecommunication inter-rack systems. For combination high reliability and low cost protocol property, we applied high level data link control (HDLC) protocol with low voltage differential signaling (LVDS) bus for card to card communicated over backplane. HDLC protocol is a high performance with several operation modes and is famous in telecommunication systems. LVDS bus is a high reliability with high immunity against electromagnetic interference (EMI) and noise. Keywords—Backplane, BLVDS, HDLC, EMI, I2C, LCT, OSC, SFP, SNMP.

Implementation of HDLC protocol based on FPGA in communication systems

A data communication system based on High-level Data Link Control(HDLC) protocol was designed,and then HDLC protocol in Field Programmable Gate Array(FPGA) was implemented.The system can take advantage of FPGA hardware effectively.It has some outstanding advantages,such as high scale integration,no need of peripheral circuit and being easy to use.This paper emphatically described the implementation methods of transmitting protocol and receiving protocol and the method for "0" bit insertion and deletion.

A Method and Its Practice for Teaching the Fundamental Technology of Communication Protocols and Coding

The education of information and communication technologies is important for engineering, and it includes terminals, communication media, transmission, switching, software, communication protocols, coding, etc. The proposed teaching method for protocols is based on the HDLC (High-level Data Link Control) procedures using our newly developed software “HDLC trainer” , and includes the extensions for understanding other protocols such as TCP/IP. As for teaching the coding theory that is applied for the error control in protocols, we use both of a mathematical programming language and a general-purpose programming language. We have practiced and evaluated the proposed teaching method in our college, and it is shown that the method has remarkable effects for understanding the fundamental technology of protocols and coding.

New Packet Synchronization System by High-Dimensional Discrete Torus Knot Code

In recent years, it is said that communication speed of next-generation cellular phones will reach 100Mbps. Accordingly, demand for robust error correction codes with high-speed processing is increasing. High-dimensional discrete torus knot code (torus code) performs well in fields with many errors. We propose a new and unique synchronization system that uses the torus code. It performs error correction and synchronization processing effectively and simultaneously. According to results of comparison with a conventional system (HDLC:High Level Data Link Control), performance (Loss of Lock Probability) of the proposed synchronization system is as much as 5 figures better than the conventional HDLC in the 10-4 field (Input BER). By applying a LSI technology, we have developed a FPGA(3Dm5, 125bit, r=0.512) with the proposed synchronization system and have built a high-speed MPEG communication device which uses the newly developed FPGA. The high-speed MPEG communication device can transmit a video signal of 20Mbps.

Hardware controls for the STAR experiment at RHIC

The STAR detector sits in a high radiation area when operating normally; therefore it was necessary to develop a robust system to remotely control all hardware. The STAR hardware controls system monitors and controls approximately 14,000 parameters in the STAR detector. Voltages, currents, temperatures, and other parameters are monitored. Effort has been minimized by the adoption of experiment-wide standards and the use of pre-packaged software tools. The system is based on the Experimental Physics and Industrial Control System (EPICS) [1]. VME processors communicate with subsystem-based sensors over a variety of field busses, with High-level Data Link Control (HDLC) being the most prevalent. Other features of the system include interfaces to accelerator and magnet control systems, a web-based archiver, and C++-based communication between STAR online, run control and hardware controls and their associated databases. The system has been designed for easy expansion as new detector elements are installed in STAR.

A simple data link protocol for high-speed packet networks

Many popular point-to-point data link protocols use the high-level data link control (HDLC) framing mechanism, which delineates protocol data units (PDUs) by means of a special bit pattern or flag. When such a flag occurs in the payload portion of a frame, an escape byte used to pad the transmitted byte stream enables the receiver to differentiate between a true framing flag and an occurrence of the flag pattern in the user information. The need to process each byte in the incoming byte stream to identify the flag pattern makes this frame delineation method increasingly more complex and expensive to implement as the interface speed increases. In addition, the byte stuffing operation performed when the flag pattern appears in the user information stream expands the carried traffic, interfering with quality of service (QoS) management procedures and making the link susceptible to malicious attacks. These factors limit the scalability and QoS management capabilities of the flag-based data link protocols, particularly at high link rates. The increasing popularity of the packet over SONET (POS) protocol stack makes it desirable to find alternative framing protocols. In this paper, we present a simple data link (SDL) protocol. Based on using a Length Indicator field and a header cyclic redundancy check (CRC), rather than a flag, to delineate frames, SDL is inherently scalable to high speeds and provides constant transmission overhead. We discuss the error control, delineation, and resynchronization mechanisms used by SDL, and we describe a link scrambler designed to protect against malicious attacks that attempt to generate very low bit transition density on the line. We also present additional link control functions designed to make SDL suitable for next-generation multiservice networks.

Communication network protocol for real-time distributed control and its LSI implementation

A new token-passing mechanism, priority token passing, which features real-time access and fast detection and recovery of transmission errors, is discussed in detail in comparison with standard token-passing protocols, and its large-scale integration (LSI)-oriented design concept is described. Priority token passing includes only a small performance overhead, due to its switching functions, which can change network topology from ring to broadcast medium. A token-holding node passes the token to another node after determining the successor through priority comparison. Errors occurring during token passing can, thus, be detected and corrected simply and promptly. Priority token passing has a simple hardware implementation, requiring only small additions to the frame control circuitry, and has a small implementation overhead. The priority token-passing protocol and two other important network communication functions, dual ring network reconfiguration and high-level data link control (HDLC) normal response mode-based message transmission, are designed as a single finite-state machine, and implemented into a compact LSI chip. This integrated instrument network (IINET) chip provides complete network communication services and requires only three additional external electronic components for operation.

Maintaining a standard

Differing interpretations of written standards are often blamed for the appearance of noncompatible equipment. A simple-to-use software package should help suppliers in one field of electronics avoid this problem. The design of a second National Motorway Communications System (NMCSZ) included high-level data link control (HDLC) protocols for the control of motorway signals. These protocols seemed to be applicable to CCTV systems and, with small modifications, were published as the new control standard in 1986. To avoid regional deviations from the standard, it was becoming necessary to have a way of measuring compliance with key parts of the standard. It was decided that a PC-based test certification package could potentially solve many of the problems. The authors discuss the development of the program including the user interface and its testing.

PAT: A protocol analysis tutor

A computer-aided learning package, PAT (protocol analysis tutor), developed as a tool to help students and novice data communications engineers learn the basic concepts of data link protocols, is described. The tool enables users to construct the frames of the HDLC (high-level data link control) standard data-link level protocol. The frames can be combined in sequence to form a call, representing the execution of the protocol. At all stages, checks of both the syntax and semantics of the call are made.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Aggregation of Systems with HDLC Protocol

AbstractThe HDLC (High‐level Data Link Control) protocol has been accepted as an international standard for computer communication networks. In this paper an aggregated mathematical model for the performance analysis of a node with HDLC protocol will be presented that is still accurate concerning mean delay and losses. The model is intended to be used as a basic element in models for networks.

Operation of HDLC abm in harsh error environments: a robust extension

The use of an extension to the high level data link control (HDLC) asynchronous balanced mode protocol to provide a reliable satellite data link service which is resilient, without operator intervention, in high levels of noise is described. Research has been directed toward providing a robust data link for the interconnections of stations using a communications satellite. Two mechanisms are described which protect the flow of control information. One is forward error correction of the control portion of the HDLC frames. The other is an extended protocol that employs redundant supervisory frames which are interleaved with the normal link traffic. The implementation of these schemes is outlined. The extended protocol is superior, providing tolerance to a wide range of error environments.

Development and performance evaluation of highly efficient retransmission scheme for high‐speed data transfer via satellite

AbstractSatellite communication has the following problems. The propagation delay is larger than in the terrestrial channel. When the carrier frequency exceeds 10 GHz, the bit‐error rate tends to increase due to the effect of rain and snow, which degrades the transmission efficiency. To cope with such problems, a highly efficient error control protocol has been proposed to prevent the degradation of the transmission efficiency.This paper describes a new large‐capacity, highly efficient retransmission scheme for satellite communication (extended SREJ scheme), which was devised considering the compatibility to the terrestrial network. The method is based on the SREJ (selective reject) scheme, which is specified in the HDLC (high‐level data link control) protocol, employed widely in terrestrial data transmission. To evaluate quantitatively REJ, SREJ and extended SREJ schemes, a satellite communication control equipment was developed.The result of the data transmission experiment is described in detail, indicating that the extended SREJ scheme is efficient. Then, through the discussion of practical usefulness, it is shown that the extended SREJ scheme has no problem from the viewpoint of the number of buffers in transmitting and receiving stations. Furthermore, to realize the efficient processing as far as possible, even if the bit‐error rate is higher than 1.0 × 10−4, the extended SREJ/REJ scheme is discussed by combining the proposed scheme with the REJ scheme.

A technique for extrapolating the end-to-end performance of HDLC links for a range of lost packet rates

A technique based on importance sampling is presented for extrapolating the end-to-end delay performance of a high-level data link control (HDLC) network. The lost packets can arise from bit errors or discarding due to network congestion. The technique works well for a substantial range of loads, as long as the desired performance is at an error rate less than the observed rate (the environment most frequently encountered). It is applicable across a range of error rates. The technique was tested on a simple HDLC link but would generalize to other link-level protocols. The extrapolation technique can be based on simulation or measurement. Simulation results are presented to demonstrate its effectiveness. >