High-level Data Link Control Protocol Research Articles

Composition Rule of Character Codes to efficiently transmit the Character Code in HDLC(High-level Data Link Control) Protocol

This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of 01111110. When data bit stream consist of the consecutive 5-bit 1 after 0, the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits 1 after 0 in the input data stream, inserts violently the 0 after 5th 1 of the consecutive 5-bit 1 after 0. As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits 1 after 0 when the code is given to each characters.

Design and Implementation of a Multi-Channel HDLC Protocol Controller Based on FPGA

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.

Backplane Serial Signaling and Protocol for Telecom Systems

In this paper, we implement a modern serial backplane platform for telecommunication inter-rack systems. For combination high reliability and low cost protocol property, we applied high level data link control (HDLC) protocol with low voltage differential signaling (LVDS) bus for card to card communicated over backplane. HDLC protocol is a high performance with several operation modes and is famous in telecommunication systems. LVDS bus is a high reliability with high immunity against electromagnetic interference (EMI) and noise. Keywords—Backplane, BLVDS, HDLC, EMI, I2C, LCT, OSC, SFP, SNMP.

Implementation of HDLC protocol based on FPGA in communication systems

A data communication system based on High-level Data Link Control(HDLC) protocol was designed,and then HDLC protocol in Field Programmable Gate Array(FPGA) was implemented.The system can take advantage of FPGA hardware effectively.It has some outstanding advantages,such as high scale integration,no need of peripheral circuit and being easy to use.This paper emphatically described the implementation methods of transmitting protocol and receiving protocol and the method for "0" bit insertion and deletion.

Aggregation of Systems with HDLC Protocol

AbstractThe HDLC (High‐level Data Link Control) protocol has been accepted as an international standard for computer communication networks. In this paper an aggregated mathematical model for the performance analysis of a node with HDLC protocol will be presented that is still accurate concerning mean delay and losses. The model is intended to be used as a basic element in models for networks.

Development and performance evaluation of highly efficient retransmission scheme for high‐speed data transfer via satellite

AbstractSatellite communication has the following problems. The propagation delay is larger than in the terrestrial channel. When the carrier frequency exceeds 10 GHz, the bit‐error rate tends to increase due to the effect of rain and snow, which degrades the transmission efficiency. To cope with such problems, a highly efficient error control protocol has been proposed to prevent the degradation of the transmission efficiency.This paper describes a new large‐capacity, highly efficient retransmission scheme for satellite communication (extended SREJ scheme), which was devised considering the compatibility to the terrestrial network. The method is based on the SREJ (selective reject) scheme, which is specified in the HDLC (high‐level data link control) protocol, employed widely in terrestrial data transmission. To evaluate quantitatively REJ, SREJ and extended SREJ schemes, a satellite communication control equipment was developed.The result of the data transmission experiment is described in detail, indicating that the extended SREJ scheme is efficient. Then, through the discussion of practical usefulness, it is shown that the extended SREJ scheme has no problem from the viewpoint of the number of buffers in transmitting and receiving stations. Furthermore, to realize the efficient processing as far as possible, even if the bit‐error rate is higher than 1.0 × 10−4, the extended SREJ/REJ scheme is discussed by combining the proposed scheme with the REJ scheme.

Specification and verification of an HDLC protocol with arm connection management and full-duplex data transfer

We use an event-driven process model to specify a version of the High-level Data Link Control (HDLC) protocol between two communicating protocol entities. The HDLC protocol is based upon the Asynchronous Response Mode (ARM) of operation, and uses the basic repertoire of HDLC commands and responses (with the exception of the CMDR response). It includes the features of poll/final cycles for connection management and checkpointing, sliding windows for data transfer, and ready/not ready messages for flow control. HDLC has three distinguishable functions: connection management, and one-way data transfers in opposite directions between the protocol entities. Various logical safety properties of the HDLC protocol concerning these functions have been verified using the method of projections.

Message Error Detecting Properties of HDLC Protocols

Upgraded requirements for data integrity and data efficiency in real-time process control applications necessitate critical investigations on existing standard data transmission conventions such as the HDLC (high level data link control) protocol. It is shown that a single bit error within an ordinary HDLC frame may cause an undetectable message error at the receiver. Further proposals for using modified HDLC protocols which guarantee the detection of single bit errors fail to detect double bit errors within a frame. Refined assessments for corresponding nondetectable message error probabilities are based on bit sequence probabilities in HDLC frames which differ slightly from bit sequences in original text fields due to the `bit escaping mechanism' required by the HDLC protocol.

HDLC Throughput and Response Time for Bidirectional Data Flow with Nonuniform Frame Sizes

The main purpose of this paper is to evaluate the performance of the HDLC (high-level data link control) protocol (to be more precise, we only consider the asynchronous response mode), and to suggest and analyze some possible improvements. The performance criteria are maximum throughput and response time and the flow of data is bidirectional with nonuniform frame sizes. The mathematical model of the HDLC protocol developed here allows us to compute its performance as a function of the maximum window width according to the characteristics of the traffic and taking into account the transmission delays and the overheads.

Performance evaluation of the HDLC protocol

The HDLC (High-Level Data Link control) protocol has been accepted as an international standard for computer communications. As such it is very important that its performance limits be well understood. The mathematical model of HDLC developed in this paper allows us to compute its performance limits as a function of window width, transmission errors, and packet lengths for symmetric and asymmetric traffics, but with no transmission delays. Explicit formulas are obtained for performance of interest such as throughput and channel activity, both in the case of selective and non-selective reject modes of operation in the presence of errors.