High-k Oxide Research Articles

Fast switching Ga2O3 Schottky barrier power diode with beveled-mesa and BaTiO3 field plate edge termination

Power devices rely on ideal edge termination to suppress the electric field crowding and avoid premature breakdown before the material's critical field is reached. In this work, a hybrid electric field management configuration, featuring the combination of beveled-mesa (BM) termination and high-k oxide BaTiO3 field plate (FP), was implemented in Ga2O3 Schottky barrier diodes (SBDs). This BMFP-SBD realizes a breakdown voltage (BV) of 1.7 kV with extremely low reverse leakage current, outperforming the BM terminated SBD with BV of 0.64 kV and bare SBD with BV of 0.22 kV. Based on the temperature-dependent reverse characteristics, the dominant leakage mechanism transforms from Poole–Frenkel (P–F) emission in BM-SBD to variable-range-hopping (VRH) in BMFP-SBD at high bias. In particular, under switching conditions of di/dt up to 420 A/μs, the BMFP-SBD exhibits superior dynamic switching characteristics with a short reverse recovery time of 10.1 ns, which are comparable with those in advanced commercial SiC SBDs. These findings underscore the potential of Ga2O3 SBD enabled by BM and high-k FP edge termination for high-speed and high-voltage power electronics applications.

Performance investigation of junction-less (JL) high-K vertical stack oxide (VSO) Ga2O3-FinFET for RF and linear applications

Performance investigation of junction-less (JL) high-K vertical stack oxide (VSO) Ga2O3-FinFET for RF and linear applications

Structural design and electronic performance at MOx/diamond (M = Hf, Zr, Ti, Al, Sc, Y) interfaces for MOS device applications

The ultra-wide bandgap semiconductor diamond represents a promising potential for advancement and innovation in the field of electronic device development. Utilizing first-principles calculations, a thorough investigation has been performed on the structural and electronic characteristics of MOx/diamond (MOx = HfO2, ZrO2, TiO2, Al2O3, Sc2O3, Y2O3) heterostructures. The concentration of charge transfer at the high-κ oxide/diamond interfaces leads to obvious interface polarity localization characteristics. The studied MOx/diamond heterojunctions feature insulating interfaces without any gap states. The MOx/diamond supercells exhibit the ability to effectively confine holes on the diamond surface owing to the large band offsets (>1 eV), showing typical electronic properties of “type II” staggered energy band configurations. These findings demonstrate that the high-κ oxide MOx/diamond can serve as highly promising diamond gate dielectrics, and provide theoretical insights into the interfacial engineering of diamond MOS devices.

Enhanced electrical performance in graphene field-effect transistors through post-annealing of high-k HfLaO gate dielectrics

High-k gate dielectrics have attracted a great deal of attention in the investigation of transistors due to their unique properties such as superior gate controllability. However, their integration into graphene field-effect transistors (GFETs) remains problematic and the physical mechanisms governing the performance of these devices are still not fully understood. In this study, the effects of post-annealing on GFETs utilizing the high-k HfLaO ternary oxide as the gate dielectric were comprehensively investigated. The HfLaO film was deposited on top of graphene by magnetron sputtering, and the device performance with various post-annealing temperatures was conducted. It was found that post-annealing temperature can effectively increase the dielectric constant through balancing the oxygen-vacancy defects and moisture absorption. Both the surface morphology of HfLaO and performance of GFETs were investigated, and the fabricated GFETs exhibit notable electrical performance enhancements. Specifically, GFETs with a 200 °C post-annealed HfLaO gate dielectric demonstrate the optimal device performance, featuring a minimal Dirac point voltage (VDirac) of 1.1 V and a minimal hysteresis (ΔVDirac) of 0.5 V. The extracted hole and electron mobilities are 4012 and 1366 cm2/V · s, respectively, nearly one order of magnitude higher than that of GFETs with as-deposited HfLaO. This work outperforms other existing GFETs utilizing high-k gate dielectric and chemical vapor deposition grown graphene in terms of both carrier mobility and on–off ratio. It is also noted that the excessive post-annealing temperature can negatively impact the GFET performance through introducing oxygen vacancies, increasing the surface roughness, lowering the breakdown voltage, and inducing recrystallization.

Structural control in atomic layer deposited hafnium oxide thin films through vertical cavity surface-emitting laser (VCSEL)-Based ultra-rapid heating

HfO2 thin films were formed by plasma-enhanced atomic layer deposition (PEALD) using TDMAHf precursor as a Hf source and oxygen plasma as an oxygen source. Rapid annealing assisted by a 980 nm wavelength vertical cavity surface-emitting laser (VCSEL) was employed to assess the dielectric properties of the HfO2 thin films, compared to furnace annealing. Operational power and time of VCSEL was precisely controlled by computational simulation. In addition to decreased thickness of the interfacial layer, rapid annealing enabled reduced leakage current density as annealing temperature increased due to suppression of crystallization, resulting from the extremely short time duration of 0.98 s–8.14 s. Cross-sectional microstructures exhibited incomplete grain boundary formation of the rapidly annealed HfO2 thin film. VCSEL-based rapid annealing was verified to be an efficient process to enhance the dielectric characteristics of high-k dielectric oxide films.

Modeling and Sensitivity Estimation of a Dual Cavity Source Pocket-Based Charge Plasma Tunneling FET for Label-Free Biological Molecule Detection

A dual-source cavity charge plasma tunneling FET (DSC-SP-CPTFET) with SiGe Pocket is proposed, and its effectiveness as a biological sensor for label-free detection is explored. The fabrication complexity and cost have been reduced by using the charge-plasma concept. For improved sensing, an etched nanocavity is added to the upper and lower of the source metal section. The high-k (HfO2) gate oxide and minimal energy gap (Si0.6Ge0.4) alloy with a 40% mole fraction improve the current sensitivity by enhancing the drain current gradient. The sensitivity of the suggested biological sensor is assessed here for several neutral biological molecules, such as Gelatin, Keratin, Biotin, and 3-Aminopropyl-Triethoxysilane (APTES). Deoxyribonucleic acid (DNA), a charged biological molecule, is also considered with varying positive and negative charge densities. The suggested biological sensor shows a (SIDS)max of 2.21 × 1010 and a Sratio of 3.11 × 109 for biological molecules with higher dielectric constant at room temperature. Different electrostatic performances are estimated in the ON state, including energy band, electron (e-) BTBT rate, electrical field, and IDS-VGS characteristics. In addition, the proposed biological sensor provides a much superior drain current sensitivity (SIDS), current ratio sensitivity (Sratio), and average SS sensitivity (SSS) performance in the presence of both charged and neutral biological molecules.

The comprehensive study of hybrid dielectric layer adopted organic thin film transistors for low voltage operation

Organic electronics hold immense promise due to their flexibility, low-cost processing, and diverse applications. Despite tremendous progress, low-voltage operation has remained a significant hurdle, impacting device efficiency. Our investigation introduces a new class of low voltage driven pentacene transistors, featuring hybrid gate insulators composed of polymer buffer layer and oxygen-plasma reacted high-k metal oxides viz. AlOx, TiOx, and TaOx. We demonstrate that a combination of titanium dioxide (TiOx) as the high-k dielectric layer and poly vinyl phenol (PVP) as a buffer layer in organic thin-film transistors (OTFTs) achieves exceptional performance compared to aluminium oxide (AlOx) and tantalum oxide (TaOx). This innovative approach yields the notable field-effect mobility (1.5 cm2/Vs) and a commendable on/off ratio (3.4 × 104), surpassing devices fabricated with other high-k oxides. The success lies in the PVP’s ability to smooth surfaces and reduce interface defects, while TiOx’s superior dielectric constant fosters stronger gate control. These findings pave the way for the development of next-generation organic devices with significantly lower operating voltages, opening doors for energy-efficient and flexible electronics.

Simultaneous electric dipoles and flat-band voltage modulation in 4H-SiC MOS capacitors through HfO2/SiO2 interface engineering

We report an approach to simultaneously tune the electric dipoles and flat-band voltage (V FB) of 4H-silicon carbide (SiC) metal-oxide-semiconductor (MOS) capacitors through high-k oxide dielectric interface engineering. With an additional HfO2 thin layer on atomic layer deposition (ALD) of SiO2 film, a dipole layer was formed at the HfO2/SiO2 interface, leading to a small positive shift of the V FB of 0.3 V in 4H-SiC MOS capacitors. The Kelvin probe method was used to examine the dipole layers induced at the direct-contact oxide/4H-SiC interfaces. It was found that a minor difference of 0.3 V in the contact potential difference (V CPD) is observed between the SiO2/4H-SiC and HfO2/SiO2/4H-SiC stacks, which signifies the presence of a weak interface dipole layer at the interface of HfO2 and SiO2. Additionally, investigation of the interface state density reveals that ALD of the HfO2 process had a negligible impact on the quality of the SiO2/4H-SiC interface, suggesting that the observed small positive V FB shift originated from the HfO2/SiO2 interface rather than the SiO2/4H-SiC interface.

Sensitivity analysis of bi-metal stacked-gate-oxide hetero-juncture tunnel fet with Si0.6Ge0.4 source biosensor considering non-ideal factors.

This article provides insights in designing a dielectrically modulated biosensor by adopting high-k stacked gate oxide proposition in a bi-metal hetero-juncture Tunnel Field Effect Transistor (BM-SO-HTFET) with Si0.6Ge0.4 source. The integrated effect of heterojunction and stacked gate oxide leads to enhanced electrical performance of the proposed device in terms of carrier mobility and suppressed leakage current. Nano-cavity engraved beneath the bi-metal gate structure across the source/channel end acts the binding site of the biomolecules to be detected. This Configuration leads to improved control of biomolecules over source/channel tunnelling rate and the same is reflected in the sensing ability of the device while extracting the ON current sensitivity (SON) of the sensor. The reported biosensor is simulated using Silvaco ATLAS calibrated simulation framework. The analysis of the device sensitivity is carried out varying dielectric constants (k) of various biomolecules, both neutral as well as charged. Our study reveals that BM-SO-HTFET with Ge mole fraction composition x = 0.4 exhibits sensitivity as high as 4.1 × 1010 for neutral biomolecules and 3.2 × 1011 for positively charged biomolecules with k = 12. Furthermore, a transient response profile for the drain current with various biomolecules is explored to determine the varying settling time. From the simulation results, it is noted that BM-SO-HTFET exhibits ON current sensitivity of 4.1 × 1010 and 3.2 × 1011 for neutral and charged biomolecules respectively. In addition to this, for highly sensitive and real time detection of biomolecules, the impact of temperature and certain non-ideal factors drifting from ideal case of fully filled cavity have also been considered to analyze its optimum sensing performance.

Efficient gradient heating-up approach for rapid growth of high-quality amorphous ZrO2 dielectric films

High-k oxide dielectric films are indispensable for low-power-consumption oxide thin-film transistors (TFTs) applied in advanced and portable electronics. However, high-quality oxide dielectric films prepared by solution process typically require sophisticated processes and long thermal annealing time, severely limiting both the throughput manufacturing and cost-effectiveness. In this study, the influence of different heating-up methods on the surface morphology and dielectric properties was systematically investigated. Gradient heating-up method could not only substantially improve the surface morphology and quality of high-k ZrO2 films but also efficiently shorten the annealing time. The gradient heating-up process was further designed on the basis of thermal behavior of the xerogel-like precursor, which successfully realize the preparation of high-quality ZrO2 films with an annealing time of 5 min (i.e. the efficiency of thermal treatment increased by about 89%). The ZrO2 film presented excellent dielectric properties, including a low leakage current density of ∼10−8 A cm−2 (at 2 MV cm−1 ), a large areal capacitance of 169 nF cm−2 and a high dielectric constant of 20.41 (1 MHz). Furthermore, InSnZnO TFT based on the ZrO2 gate dielectrics shows an acceptable device performances, such as a high carrier mobility of 2.82 cm2 V−1 s, a high on/off current ratio of ∼105 and a low subthreshold swing of 0.19 V decade −1 at a low operation voltage of 5 V. This work provide a highly promising approach to fabricate high-quality solution-processed high-k oxide dielectric films employed for large-scale and low-power-consumption electronics.

Realization of CO2 gas sensors and broadband photodetectors using metal/high-k CeO2/p-Si heterojunction

Realization of high-k dielectric oxide material-based devices such as photodetectors (PDs)/gas sensors fabricated on silicon substrate seems to be the utmost promising as a cost-effective approach to use in next generation optoelectronic field. We have explored metal/CeO2/p-Si heterojunction to construct as a broadband (BB) PD and CO2 gas sensor device. The effect of post-annealing procedure on photodetection and CO2 gas sensing characteristics were correlated using AFM, XRD, XPS, Raman and UV–Vis studies. At 0 V bias, the fabricated as-deposited Au/CeO2/p-Si PD device exhibits outstanding performance with enhanced responsivity of 85 AW−1 (at 910 nm), detectivity of 1.36×1015 Jones (at 850 nm), EQE of 1.3×104 % (at 850 nm), faster rise and fall times of 124 ms and 107 ms (at 900 nm). On the other hand, the photodetection characteristic parameters were slightly deteriorated as a function of annealing with respect to the as-deposited device. One of the causes for this fact was attributed to the increase in rms surface roughness (AFM) and decrease in absorbance of CeO2 thin film (UV–Vis). Additionally, Ag/CeO2/p-Si heterojunction was studied as a CO2 gas sensor and evaluated response/recovery times as a function of CO2 gas concentration. Sensing responses of CeO2 as-deposited, CeO2-400, CeO2-500, CeO2-600 and CeO2-700 °C were around 58, 60, 62, 81 and 90 %, respectively, when exposed to 200 ppm of CO2. Thus, we validate that the prospect of integrating enhanced performance in BB PDs and CO2 gas sensors using metal/CeO2/p-Si heterojunction could serve as a basic building block in near future optoelectronic applications. Furthermore, the effect of post-annealing temperature on the morphological, structural, BB photodetection and CO2 gas sensing properties were discussed in detail.

Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO2) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO2/Si metal-oxide-semiconductor (MOS) devices. The high-k CeO2 thin films were deposited by spin-coating and sintered at different annealing temperatures (Ta) in the range of 400–900 °C. The parameters such as fixed charge density (Qeff), dielectric constant (k) of the layers, flat-band voltage (VFB), interface defect density (Dit), etc., of the MOS device were evaluated from CV and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Qeff (−4.81 × 1011 C/cm2) have been achieved for the Ta of 600 °C. The k and Dit were evaluated to be 22 and 1.29 × 1012 cm−2, respectively at the Ta of 600 °C. In addition, the CV measurements showed a very small hysteresis and very low frequency dispersion for the Ta of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO2 layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at Ta of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO2 films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO2 layers suitable for MOS like devices.

DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy.

This study developed a DC-free technique that used dark-mode scanning capacitance microscopy (DM-SCM) with a small-area contact electrode to evaluate and image equivalent oxide thicknesses (EOTs). In contrast to the conventional capacitance-voltage (C-V) method, which requires a large-area contact electrode and DC voltage sweeping to provide reliable C-V curves from which the EOT can be determined, the proposed method enabled the evaluation of the EOT to a few nanometers for thermal and high-k oxides. The signal intensity equation defining the voltage modulation efficiency in scanning capacitance microscopy (SCM) indicates that thermal oxide films on silicon can serve as calibration references for the establishment of a linear relationship between the SCM signal ratio and the EOT ratio; the EOT is then determined from this relationship. Experimental results for thermal oxide films demonstrated that the EOT obtained using the DM-SCM approach closely matched the value obtained using the typical C-V method for frequencies ranging from 90 kHz to 1 MHz. The percentage differences in EOT values between the C-V and SCM measurements were smaller than 0.5%. For high-k oxide films, DM-SCM with a DC-free operation may mitigate the effect of DC voltages on evaluations of EOTs. In addition, image operations were performed to obtain EOT images showing the EOT variation induced by DC-stress-induced charge trapping. Compared with the typical C-V method, the proposed DM-SCM approach not only provides a DC-free approach for EOT evaluation, but also offers a valuable opportunity to visualize the EOT distribution before and after the application of DC stress.

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.

Theoretical Insight into the Band Alignment at High-κ Oxide XO2/Diamond (X = Hf and Zr) Interfaces with a SiO2 Interlayer for MOS Devices.

Diamond has become a promising candidate for high-power devices based on its ultrawide bandgap and excellent thermoelectric properties, where an appropriate gate dielectric has been a bottleneck hindering the development of diamond devices. Herein, we have systematically investigated the structural arrangement and electronic properties of diamond/high-κ oxide (HfO2, ZrO2) heterojunctions by first-principles calculations with a SiO2 interlayer. Charge analysis reveals that the C-Si bonding interface attracts a large amount of charge concentrated at the diamond interface, indicating the potential for the formation of a 2D hole gas (2DHG). The diamond/HfO2 and diamond/ZrO2 heterostructures exhibit similar "Type II" band alignments with VBOs of 2.47 and 2.21 eV, respectively, which is consistent with experimental predictions. The introduction of a SiO2 dielectric layer into the diamond/SiO2/high-κ stacks exhibits the typical "Type I″ straddling band offsets (BOs). In addition, the wide bandgap SiO2 interlayer keeps the valence band maximum (VBM) and conduction band minimum (CBM) in the stacks away from those of diamond, effectively confining the electrons and holes in MOS devices. This work exhibits the potential of SiO2/high-κ oxide gate dielectrics for diamond devices and provides theoretical insights into the rational design of high-quality gate dielectrics for diamond-based MOS device applications.

High-κ Oxide Charge Engineering on GaN for Normally Off HEMTs

High-κ Oxide Charge Engineering on GaN for Normally Off HEMTs

Integrated 2D multi-fin field-effect transistors

Vertical semiconducting fins integrated with high-κ oxide dielectrics have been at the centre of the key device architecture that has promoted advanced transistor scaling during the last decades. Single-fin channels based on two-dimensional (2D) semiconductors are expected to offer unique advantages in achieving sub-1 nm fin-width and atomically flat interfaces, resulting in superior performance and potentially high-density integration. However, multi-fin structures integrated with high-κ dielectrics are commonly required to achieve higher electrical performance and integration density. Here we report a ledge-guided epitaxy strategy for growing high-density, mono-oriented 2D Bi2O2Se fin arrays that can be used to fabricate integrated 2D multi-fin field-effect transistors. Aligned substrate steps enabled precise control of both nucleation sites and orientation of 2D fin arrays. Multi-channel 2D fin field-effect transistors based on epitaxially integrated 2D Bi2O2Se/Bi2SeO5 fin-oxide heterostructures were fabricated, exhibiting an on/off current ratio greater than 106, high on-state current, low off-state current, and high durability. 2D multi-fin channel arrays integrated with high-κ oxide dielectrics offer a strategy to improve the device performance and integration density in ultrascaled 2D electronics.

Bias-stress-stable sub-1.5V oxide thin-film transistors via synergistic composition of sol-gel quaternary high-k oxide dielectrics

A rising demand in reliable, energy-efficient, and large-area electronics, particularly in the realm of sol-gel oxide thin-film transistors (TFTs), has steered research focus away from semiconductor towards dielectrics. However, achieving both bias stability and low-voltage operation remains a significant hurdle. While typical oxide TFTs employ high-dielectric-constant (high-k) dielectrics with lowered film thickness to acquire low-voltage operation, they inevitably suffer from undesired defects at both bulk and interfacial trap sites in dielectric layer. In this study, bias-stress-stable all solution-processed oxide TFTs were demonstrated with operation voltage under 1.5 V via sol-gel quaternary high-k oxide dielectric (Al-Hf-Zr-O, AHZO). In-depth understanding of their individual contributions to dielectric performance leads to the acquisition of optimized composition ratios of AHZO with amorphous feature and outstanding dielectric performance, marked by dielectric constant (k) over 11, leakage current density (Jleak) below 10−5.5 A cm−2, and sturdy breakdown strength (EB) exceeding 5 MV cm−1. By integrating the AHZO with In-Ga-Zn-O (IGZO) layer, we achieved sub 1.5 V TFTs while maintaining excellent bias stability with threshold voltage (VTH) shift lower than 0.20 V for 3600 s. Our findings offer a detailed insight into the realm of multi-component oxide dielectrics, paving the way for miniaturization and reliability in functional devices and sensors.

Flexible and Energy-Efficient Synaptic Transistor with Quasi-Linear Weight Update Protocol by Inkjet Printing of Orientated Polar-Electret/High-k Oxide Composite Dielectric.

Inkjet printing artificial synapse is cost-effective but challenging in emulating synaptic dynamics with a sufficient number of effective weight states under ultralow voltage spiking operation. A synaptic transistor gated by inkjet-printed composite dielectric of polar-electret polyvinylpyrrolidone (PVP) and high-k zirconia oxide (ZrOx) is proposed and thus synthesized to solve this issue. Quasi-linear weight update with a large variation margin is obtained through the coupling effect and the facilitation of dipole orientation, which can be attributed to the orderly arranged molecule chains induced by the carefully designed microfluidic flows. Crucial features of biological synapses including long-term plasticity, spike-timing-dependence-plasticity (STDP), "Learning-Experience" behavior, and ultralow energy consumption (<10 fJ/pulse) are successfully implemented on the device. Simulation results exhibit an excellent image recognition accuracy (97.1%) after 15 training epochs, which is the highest for printed synaptic transistors. Moreover, the device sustained excellent endurance against bending tests with radius down to 8 mm. This work presents a very viable solution for constructing the futuristic flexible and low-cost neural systems.

A comparative study on 2D materials with native high-[formula omitted] oxides for sub-10 nm transistors

Two-dimensional (2D) transition metal dichalcogenides (TMDs) with native high-κ oxides have presented a new avenue towards the development of next-generation ultra-scaled field-effect transistors (FETs). These materials have been experimentally shown to form a natively compatible oxide layer with a high dielectric constant, which can help scale down both the transistor size and the supply voltage. We present a material and device performance study into the use of several of these materials – namely HfS2, HfSe2, ZrS2, ZrSe2 – as channels in sub-10 nm FETs. All four materials exhibit isotropic transport at 10 nm channel length with ON currents over 1000 μA/μm but show anisotropic transport and degraded ON currents at 5 nm channel length. In general, the sulfide family excels in terms of subthreshold characteristics at sub-10 nm channel lengths. HfS2, in particular, surpasses all the other materials in terms of ON currents and subthreshold swing (SS), allowing it to also achieve excellent intrinsic performance. We have identified HfS2 as a superior material within this TMD family for sub-10 nm FETs.