High Inversion Channel Mobility Research Articles

Effect of Shallow n-Doping on Field Effect Mobility in p-Doped Channels of 4H-SiC MOS Field Effect Transistors

A high inversion channel mobility is a key parameter of normally off Silicon-Carbide MOS field effect power transistors. The mobility is limited by scattering centers at the interface between the semiconductor and the gate-oxide. In this work we investigate the mobility of lateral normally-off MOSFETs with different p-doping concentrations in the channel. Additionally the effect of a shallow counter n-doping at the interface on the mobility was determined and, finally, the properties of interface traps with the charge pumping method were examined. A lower p-doping in the cannel reduces the threshold voltage and increases the mobility simultaneously. A shallow counter n-doping shows a similar effect, but differences in the behavior of the charge pumping current can be observed, indicating that the nitrogen has a significant effect on the electrical properties of the interface, too.

Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide

We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s by POCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> annealing at 1000°C.

Improved Inversion Channel Mobility in Si-face 4H-SiC MOSFETs by Phosphorus Incorporation Technique

AbstractWe propose a new technique to fabricate 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO2/4H-SiC(0001) interface by post-oxidation annealing using phosphoryl chloride (POCl3). The interface state density at 0.2 eV from the conduction band edge was reduced to less than 1 × 1011 cm−2eV−1 by the POCl3 annealing at 1000 °C. The peak field-effect mobility of 4H-SiC MOSFETs on (0001) Si-face processed with POCl3 annealing at 1000 °C was approximately 90 cm2/Vs. The high channel mobility is attributed to the reduced interface state density near the conduction band edge.

Atomistic Scale Modeling and Analysis of Sodium Enhanced Oxidation of Silicon Carbide

We explain the phenomenon of sodium enhanced oxidation (SEO) using computational techniques, and analyze a set of probable hypotheses, which can elucidate the observation of high inversion channel mobility achieved with SEO. The ability of the Na to screen the interface traps, reduce carbon cluster type of defect formation, and enhance the oxidation rate can be explained using these calculations. We observe an increased availability of electrons near the interface in the presence of Na. The sodium atom also helps in breaking the intramolecular oxygen bond. The electronic and atomic structure of the interface cluster, and electric field computations showed that the carbon cluster formed at the oxide side of the interface could be screened by the Na ion.

Sodium Enhanced Oxidation of Si-Face 4H-SiC: A Method to Remove Near Interface Traps

We demonstrate how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2/4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1-10 cm2/Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these nearinterface traps resulting in high inversion channel mobility of 150 cm2/Vs in such transistors. Sodium can be incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during formation of the SiC/SiO2 interface.

A strong reduction in the density of near-interface traps at the SiO2∕4H-SiC interface by sodium enhanced oxidation

This paper demonstrates how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2∕4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1–10cm2∕Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these near-interface traps resulting in high inversion channel mobility of 150cm2∕Vs in such transistors. Sodium is incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during the formation of the SiC∕SiO2 interface.

Comparison between oxidation processes used to obtain the high inversion channel mobility in 4H-SiC MOSFETs

In this work two oxidation methods aimed at improving the silicon face 4H-SiC/SiO2 interface are compared. One is an oxidation in N2O performed in a quartz tube using quartz sample holders and the other is a dry oxidation performed in an alumina tube using alumina sample holders. In n-type metal oxide semiconductor (MOS) capacitors the interface state density near the SiC conduction band edge is estimated using capacitance–voltage (C–V) and thermal dielectric relaxation current (TDRC) measurements. N-channel metal oxide semiconductor field effect transistors (MOSFETs) are characterized by current–voltage (I–V) techniques and the inversion channel mobility is extracted. It is shown that the high inversion channel mobility (154 cm2 V−1 s−1) seen in samples oxidized using alumina correlates with a low interface trap density (3.6 × 1011 cm−2). In the case of N2O oxidation the mobility is lower (24 cm2 V−1 s−1) and the interface trap density is higher (1.6 × 1012 cm−2). Room temperature C–V measurements are of limited use when studying traps near the conduction band edge in MOS structures while the TDRC measurement technique gives a better estimate of their density.

High Inversion Channel Mobility of 4H-SiC MOSFETs Fabricated on C(000-1) Epitaxial Substrate with Vicinal (Below 1º) Off-Angle

SiC power MOSFETs are expected to be normally-off type fast switching devices. The on-resistance of SiC power MOSFETs is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface state density (Dit). We have already reported that 4H-SiC MOSFETs on the C(0001 _ ) face had higher inversion-channel mobility. However, there is the SiO2/SiC interface roughness problem in SiC MOSFETs. There are many steps at the SiO2/SiC interface because a high off-angle is necessary for SiC epitaxial growth. These steps might make SiO2/SiC interfaces rough, which leads to reduction of channel mobility. In this work, we have investigated the effect of the SiO2/SiC interface roughness caused by the off-angle on the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(0001 _ ) face. The inversion-channel mobility of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the vicinal off-angle(0.8°) is higher than that of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the 8° off-angle. Reduction of the off-angle is very useful for improvement of channel mobility. A C(0001 _ ) epitaxial substrate with the vicinal off-angle would be suitable for SiC DMOSFETs.

Effects of chlorine on interfacial properties and reliability of SiO2 grown on 6H-SiC

A new process of oxidizing 6H-SiC in dry O2+trichloroethylene (TCE) is used to incorporate chlorine in SiO2. The interface quality and the reliability of 6H-SiC MOS capacitors with gate dielectrics prepared by the process are examined. As compared to the conventional dry O2 oxidation, the O2+TCE oxidation results in lower interface-state density, reduced oxide-charge density and enhanced reliability. This could be attributed to the passivation effects of Cl2 and HCl on the structural defects at/near the SiC/SiO2 interface, and also their gettering effects on ion contamination. Moreover, post-oxidation NO annealing, especially in a wet ambient, can further decrease the interface-state density and the oxide-charge density. Lastly, an increased oxidation rate induced by TCE is observed and should be useful for reducing the normally high thermal budget of oxide growth. All these are very attractive for fabricating SiC MOSFETs with high inversion-channel mobility and high hot-carrier reliability.

Interfacial properties and reliability of SiO2 grown on 6H-SiC in dry O2 plus trichloroethylene

A new process of growing SiO2 on n- and p-type 6H-SiC wafers in dry O2+trichloroethylene (TCE) was investigated. The interface quality and reliability of 6H-SiC metal-oxide-semiconductor (MOS) capacitors with gate dielectrics prepared by the process were examined. As compared to conventional dry O2 oxidation, the O2+TCE oxidation resulted in lower interface-state, border-trap and oxide-charge densities, and enhanced reliability. This could be attributed to the passivation effect of Cl2 or HCl on structural defects at/near the SiC/SiO2 interface, and the gettering effect of Cl2 or HCl on ion contamination. In addition, increased oxidation rate was observed in the O2+TCE ambient, and can be used to reduce the normally-high thermal budget for oxide growth. All these are very attractive for fabricating SiC MOS field-effect transistors (MOSFETs) with high inversion-channel mobility and high hot-carrier reliability.