High DC Gain Research Articles

A pipelined SAR ADC with gain-stage based on capacitive charge pump

This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

High Gain DC–DC Converter Based on the Cockcroft–Walton Multiplier

Recent advancements in renewable energy have created a need for both high step-up and high-efficiency dc-dc converters. These needs have typically been addressed with converters using high-frequency transformers to achieve the desired gain. The transformer design, however, is challenging. This paper presents a high step-up current fed converter based on the classical Cockcroft-Walton (CW) multiplier. The capacitor ladder allows for high voltage gains without a transformer. The cascaded structure limits the voltage stresses in the converter stages, even for high gains. Being current-fed, the converter (unlike traditional CW multipliers) allows the output voltage to be efficiently controlled. In addition, the converter supports multiple input operation without modifying the topology. This makes the converter especially suitable for photovoltaic applications where high gain, high efficiency, small converter size, and maximum power point tracking are required. Design equations, a dynamic model, and possible control algorithms are presented. The converter operation was verified using digital simulation and a 450-W prototype converter.

Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

Performance evaluation of interleaved high‐gain converter configurations

This study presents the experimental verification of an interleaved high-gain (IHG) DC–DC converter using series and parallel configurations. The interleaved configurations allow the converter to achieve high voltage gain and high current rating, thus increasing the power rating of the converter. Analytical expressions for the design of these interleaved converter configurations are included in the study. The efficiency of the IHG DC–DC converter is increased due to the zero-voltage switching of all active switches and the zero-current switching of all diodes. Experimental results taken from three 1 kW prototypes with different configuration (non-interleaved, and series and parallel interleaved) are presented to verify the interleaving performance and efficiency. Moreover, the effect of soft-switching in terms of efficiency is demonstrated.

Low Power and High Gain Operational Transconductance Amplifier

A Positive feedback method for operational transconductance amplifiers is proposed operating at subthreshold region. In this paper a differential amplifier has designed with gain enhancement technique using positive feedback. The proposed circuit has improved specifications such as high DC gain, low power dissipation as compared to previous work. We designed CMOS OTA in a UMC 180nm technology powered with 1.8V exhibits 91.23-dB DC gain while consuming 35.72nW.

Coupled inductor‐based single‐stage high gain DC–AC buck–boost inverter

Two stage conversion systems (TSCSs) normally use either boost converter or high gain dc-dc converter along with dc-ac inverter in order to transfer power from low input voltage dc source to high voltage ac load. When these TSCSs operate at extremely low input voltages, the boost converter has to operate at extremely high duty ratios. This in turn results in more losses and reverse recovery problems. Usage of high gain dc-dc converter results in more number of components, increase in control complexity and decrease in reliability. Single-stage conversion systems (SSCSs) are formed by merging both dc-dc and dc-ac conversion processes. These SSCSs have advantages like low loss, more compactness and less reverse recovery problems. In this study, a high gain coupled inductor-based single-phase SSCS is presented. This SSCS topology has many desirable features such as high gain, less switching losses, free from leakage inductance adverse effects and compact. Principle of operation, steady-state analysis and design of the proposed topology are described in detail. MATLAB simulation results of the proposed topology and experimental results using DSP28335-based experimental setup are presented to validate the proposed scheme.

Transformerless high‐gain DC–DC converter for microgrids

This study proposes a novel non-isolated high-gain high-power DC–DC converter. The converter is developed from a basic high-gain high-power converter structure. The proposed converter comprises of a three-phase interleaved boost converter, one coupled inductor and a voltage multiplier cell which act as gain extension stage. The main desirable features like voltage gain, stress on the switches and diodes, turns ratio, component utilisation factor and efficiency are summarised. The power circuit, operational details, simulation and experimental results of the 60 V/1.1 kV, 3 kW, 100 kHz proposed converter are presented.

A Low-Dropout Voltage Regulator with a Fractional-Order Control

This paper presents a 5 V / 50 mA low-dropout voltage regulator (LDO). The LDO uses a fractional-order control for its regulation loop to achieve a high DC gain (for a tight DC regulation) while avoiding (for a good stability) a high gain at high frequency. No compensation zeros are needed. The unity gain frequency of the regula- tion loop also changes adaptively with the output current to maintain it below the frequency of non-dominant poles. The LDO is stable with any external capacitance larger than 50 nF, and is expected to operate in a harsh automo- tive environment, with junction temperature ranging from -40°C to 170°C and with supply voltage from 7 V to 36 V. The operation of the LDO has been verified by realizing it in the 350 nm I3T50 ON Semiconductor technology.

High DC gain self‐cascode structure of OTA design with bandwidth enhancement

A high DC gain self-cascode structure of operational transconductance amplifier (OTA) design with bandwidth enhancement is proposed. Based on the concept of self-cascode structure, which provides high output resistance and transconductance, the proposed OTA presents a compensation methodology to obtain better unity-gain bandwidth. The proposed OTA is compared with previous structures, with the same size of input/output transistors and compensation capacitance as well as load capacitance, and simulation results show a DC gain enhancement of >20% and 2.4 times unity-gain bandwidth at the same time, and the performances of the proposed OTA bring a better figure of merit (FOM).

A high speed four-stage operational amplifier in 65 nm CMOS

The paper presents a four-stage operational amplifier (OPA) with high DC gain and large bandwidth by combining no capacitor feedforward compensation and reversed nested indirect compensation. The p...

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English

A full W-band low noise amplifier module for millimeter-wave applications**Project supported by the Major Program of the National Natural Science Foundation of China (No. 61434006) and the National Natural Science Foundation of China (No. 61401457).

A full W-band low noise amplifier (LNA) module is designed and fabricated. A broadband transition is introduced in this module. The proposed transition is designed, optimized based on the results from numerical simulations. The results show that 1 dB bandwidth of the transition ranges from 61 to 117 GHz. For the purpose of verification, two transitions in back-to-back connection are measured. The results show that transmission loss is only about 0.9–1.7 dB. This transition is used to interface integrated circuits to waveguide components. The characteristic of the LNA module is measured after assembly. It exhibits a broad bandwidth of 75 to 110 GHz, and has a small signal gain above 21 dB. The noise figure is lower than 5.2 dB throughout the entire W-band (below 3 dB from 89 to 95 GHz) at room temperature. The proposed LNA module exhibits potential for millimeter wave applications due to its high small signal gain, low noise, and low DC power consumption.

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an Nth-order IADC close to that of a (2N-1)th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and it consumes only 10.7 μW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

Performance Analysis of Transformer-Less Two Phase Interleaved High Gain DC Converter using MPPT Algorithm

Objectives: The performance of parallel input and series output configured interleaved high gain DC converter using MPPT algorithm is analyzed. Methods: The output power of PV varies due to change in temperature and irradiation levels. This reduces the conversion efficiency. Hence, Perturb and Observe (P&O) algorithm is used to achieve maximum power from PV panel with suitable duty ratio and also improves efficiency. The simulations are carried out using MATLAB/SIMULINK to validate the operation and effectiveness of the converter using MPPT algorithm. Results: The transformer-less two phase interleaved converter not only produces high output voltage but also reduces voltage stress of active switches. The simulation results for the converter using P&O algorithm is presented in this paper. The various parameters such as output current, output voltage and output power of the transformer-less two phase interleaved DC converter were compared with and without MPPT. Conclusion and Application: The converter with MPPT produces an output of 248.2 W which is 1.1 times that of converter without MPPT. Thus, the two phase’s interleaved DC converter with MPPT shows better performance and can be used for standalone applications.

Efficiency comparison between Si and SiC‐based implementations in a high gain DC–DC boost converter

An efficiency comparison between a boost converter implemented with silicon (Si) devices and the same converter implemented in the other three cases, that is, employing two combinations of silicon carbide (SiC) devices and a mixture of Si and SiC elements is presented. The converter has been designed for high-voltage low-power applications required by light-emitting diode (LED) lighting. The comparison is performed on an equal basis and discusses the influence on the converter efficiency of the semiconductor power devices and the passive components. The experiments are carried out in a single-stage boost converter prototype delivering a maximum output voltage of 1200 V when supplied by a 12 V battery. The measurements show that the highest efficiency is obtained when the power transistor is implemented by a normally-off junction field-effect transistor and the diode by a SiC Schottky device with a small parasitic capacitance. The implementation with the highest efficiency has been selected for supplying a light spot of 320 LEDs in series, which results in an output voltage of 956 V and an output power of 20.6 W.

Improving power efficiency of a two-stage operational amplifier for biomedical applications

By using compensation technique with feed-forward path, an improved folded cascode operational transconductance amplifier (OTA) that operates in weak inversion region is designed. The proposed configuration consists of composite transistors, recycling structure and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity gain frequency and slew rate without adversely affecting the noise and offset performance. The presented OTA is simulated in 0.18 μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 104.5 dB open-loop DC gain and 69.4 kHz unity gain frequency @ 0.6 V supply voltage while the power consumption is 300 nW.

Robust Sliding-Mode Control Design for a Voltage Regulated Quadratic Boost Converter

A robust controller design to obtain output voltage regulation in a quadratic boost converter with high dc gain is discussed in this paper. The proposed controller has an inner loop based on sliding-mode control whose sliding surface is defined for the input inductor current. The current reference value of the sliding surface is modified by a proportional-integral compensator in an outer loop that operates over the output voltage error. The stability of the two-loop controller is proved by using the Routh-Hurwitz criterion, which determines a region in the K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> -K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</sub> plane, where the closed-loop system is always stable. The analysis of the sliding-mode-based control loop is performed by means of the equivalent control method, while the outer loop compensator is derived by means of the Nyquist-based Robust Loop Shaping approach with the M-constrained Integral Gain Maximization technique. Robustness is analyzed in depth taking into account the parameter variation related with the operation of the converter in different equilibrium points. Simulations and experimental results are presented to validate the approach for a 20-100-W quadratic boost converter stepping-up a low dc voltage (15-25-V dc) to a 400-V dc level.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

A Cascode Miller-Compensated Three-Stage Amplifier With Local Impedance Attenuation for Optimized Complex-Pole Control

This work presents a power- and area-efficient three-stage amplifier that is able to drive a large capacitive load. Removing the inner Miller capacitor and employing cascode Miller compensation in the outer compensation loop could extend the complex-pole frequency of a three-stage amplifier, but result in a high Q-factor. A local impedance attenuation block consisting of a series RC network is proposed to control the complex poles. This block attenuates the high-frequency resistance at the second-stage output and achieves an optimized tradeoff between the frequency and the Q-factor of the complex poles. As the low-frequency resistance remains unchanged, a high dc gain is maintained. Implemented in 0.13 $\mu$ m CMOS process, the proposed design occupies an area of 0.0032 mm 2 and consumes a quiescent current of 10.5 $\mu$ A. When driving a 560 pF capacitive load, it achieves a unity-gain frequency of 3.49 MHz, an average slew rate of 0.86 V/ $\mu$ s, and an average settling time of 0.9 $\mu$ s.

A Method to Simulate Treatment of Thyroid Problems in the Human Body

This is an effort to simulate the concept of treatment of different types of Thyroidism after determining the TSH, T3 and T4 levels in the human body. The target is to determine the effective dose of Thyroxine to be provided to the patient so that normal level of the same can be maintained in the human body. It interacts with every organ system and plays a crucial role in metabolism [1], but there is no software technique to bypass the doctors for the treatment of Thyroid malfunctioning. The Analog devices like operational amplifiers have features identical to the arithmetic operations. Primarily, the voltages in the high-gain dc amplifiers can be reduced to an average to these three variables and the operational amplifiers can do the arithmetic operations on the voltages, the accuracy of measuring voltage may be circumscribed to limited point. A Digital circuit has been implemented to determine the dosage required by the patients using the best market products. The simulation has been done using CircuitMaker ( Student version).