High Frequency Ring Oscillator Research Articles

A versatile architecture for long-term monitoring of single-event transient durations

We present design and analysis of an on-chip measurement infrastructure, which facilitates long-term monitoring of single-event transient durations in digital VLSI circuits exposed to uncontrollable radiation. Unlike the known oscilloscope-based methods, our approach is all-digital: SET durations are measured by the SET-gated counting of pulses generated by a high-frequency ring oscillator, and stored in an up/down-counter array organized in a ring. We carefully elaborate a comprehensive concept for making our infrastructure SEU tolerant, with the main challenge being to attain a sufficiently high probability of recording useful hits in the target before exhausting the SEU tolerance of the infrastructure. Our key contribution here concerns the protection of the counter array: Rather than resorting to radiation hardening or explicit triple modular redundancy (TMR), we save area by using a novel redundant duplex counter architecture: For a small number of recorded SETs, our architecture implicitly implements TMR, albeit in a way that degrades gracefully for larger numbers of recorded SETs. Besides standard functional and timing verification, we use Spice-based SET injection for verifying the effectiveness of our SEU-tolerant architecture, and some cross section-based probabilistic analysis for confirming that our measurement infrastructure based on it indeed achieves its purpose.

DESIGN OF RING VCO USING NINE STAGES OF DIFFERENTIAL AMPLIFIER

The proposed ring oscillator is fundamentally constructed by cascading series of delay cells, complying with the Barkhausen oscillation criterion of gain and phase shift. Focusing the need of low voltage design, which leads to an increased delay cell integration The number of delay cell reflects a high speed with low power consumption. Barkhausen criterion highlights the need of increased number of cascade differential amplifier based delay cell. To overcome the constraint of power dissipation, VCOs with reduced number of delay stages and the operation of sub threshold region has been widely used. In this paper a low power voltage controlled ring oscillator is implemented using the 250nm CMOS technology provided by generic with 2.5 volt power supply. The circuit is a modification of conventional ring oscillator. In favor of easy implementation of the module in small die size a nine stages of differential amplifier has been adopted to fabricate the proposed VCRO. The optimization design are done using S-EDIT software to make the oscillator as small as possible. In, addition Tanner tools is used in the analysis and simulation to verify the predicted performance. The proposed design is suitable for PLL and Timer circuits. The optimized ring oscillator is then compared with the previous design done by other researchers. The existence of various topologies of high-frequency ring oscillator highlight an essential design breakthrough optimizing to the power dissipation and tuning range of 125 MHz-561.798 MHz. The ring oscillator is able to operate with 2.5v supply and consuming around 3.6mwatt.

Low Voltage and High Oscillation Frequency Gated Ring Oscillator Using Bootstrap Technique

In this paper, a high frequency ring oscillator with low power consumption is proposed.The proposed ring oscillator is based on GRO by applying boot strap technique. Simulation resultsindicate that the FoM(Power Consumption/Oscillation Frequency) of the proposed ring oscillator isless than that of the conventional ring oscillator.

Producing Random Bits with Delay-Line-Based Ring Oscillators

Abstract One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.

A 6.0–13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS

A 6.0-13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply.

Investigation of a high frequency CMOS unsaturated ring oscillator

Investigation of a high frequency unsaturated ring oscillator with cross coupled load is presented, and oscillation frequency compared with multi-path high frequency ring oscillators. Stability of ...

A low power and small area all digital delay-locked loop based on ring oscillator architecture

A 133–500 MHz, 5.2 mW@500 MHz, 0.021 mm2 all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.

Nanowire Transistor Performance Limits and Applications

Semiconductor nanowires represent unique materials for exploring phenomena at the nanoscale. Developments in nanowire growth have led to the demonstration of a wide range of nanowire materials with precise control of composition, morphology, and electrical properties, and it is believed that this excellent control together with small channel size could yield device performance exceeding that obtained using top-down techniques. Here, we review advances in chemically synthesized semiconductor nanowires as nanoelectronic devices. We first introduce basic nanowire field-effect transistor structures and review results obtained from both p- and n-channel homogeneous composition nanowires. Second, we describe nanowire heterostructures, show that by using nanowire heterostructures, several limiting factors in homogeneous nanowire devices can be mitigated, and demonstrate that nanowire transistor performance can reach the ballistic limit and exceed state-of-the-art planar devices. Third, we discuss basic methods for organization of nanowires necessary for fabricating arrays of device and circuits. Fourth, we introduce the concept of crossbar nanowire circuits, discuss results for both transistor and nonvolatile switch devices, and describe unique approaches for multiplexing/demultiplexing enabled by synthetically coded nanowire. Fifth, we discuss the unique application of thin-film nanowire transistor arrays on low-cost substrates and illustrate this with results for relatively high-frequency ring oscillators and completely transparent device arrays. Finally, we describe 3-D heterogeneous integration that is uniquely enabled by multifunctional nanowires within a bottom-up approach.

An Analytical Equation for the Oscillation Frequency of High-Frequency Ring Oscillators

An analytical equation for the oscillation frequency of a ring oscillator is derived. The derivation is done using a novel method which does not need to find an expression for the delay of each stage. The resulting equation includes the effect of time-varying parasitics. It also includes the effect of the gate resistance, which has a large effect on the oscillation frequency at high frequencies. Measurement results of ring oscillators fabricated in a 0.18-/spl mu/m CMOS process show that the resulting equation has an average error of 8% over a large range of parameter variations.