High Frequency Interconnects Research Articles

Analysis and Characterization of Castellated Holes as RF Interconnects for Modular Millimeter-Wave Devices

This paper presents an innovative approach to the use of Castellated Holes or Plated Half Holes (PHH) as transmission elements for high frequency interconnections between printed circuit boards in a frequency range of up to 40 GHz. The basic design was examined using commonly used design parameters for PCB modules with Castellated Holes which were then investigated and subsequently optimized to improve their RF performance, with a particular focus on design considerations according to today’s industrial manufacturing capabilities. Therefore the FEM-based full wave simulation technique was used to compare and optimize the design parameters in the aim to improve the capability of PHHs as low-loss, low-disturbant RF interconnection alternative in modular PCB designs. Based on these results test samples were developed, which were subsequently measured and thus verified the findings of the simulation. To provide a general comparability, this study focused on the S-Parameter to quantify the performance in terms of transmission losses and reflection. With an optimized design feasible results were achieved with a maximum transmission loss of less than 2 dB at the maximum of the desired frequency range and about 1dB at 20 GHz over the entire signal path. These insights make PHHs suitable for seamless integration into modular designs in RF and millimeter-wave applications.

Wireless Network On-Chips History-Based Traffic Prediction for Token Flow Control and Allocation

Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms.

Performance Evaluation of Centralized Reconfigurable Transmitting Power Scheme in Wireless Network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication among all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. This paper evaluates the energy and latency performance of a closed loop power management mechanism which enables transmitting power reconfiguration in WiNoC based on number of erroneous received packets. The scheme achieves significant energy savings with limited performance degradation and insignificant impact on throughput.

The effect of metal-contacts on carbon nanotube for high frequency interconnects and devices

High frequency characterisation of platinum and tungsten contacts on individual multi-walled carbon nanotubes (MWNT) is performed from 10 MHz to 50 GHz. By measuring the scattering parameters of aligned individual MWNTs, we show that metal contacts enhance an inductive response due to the improved MWNT-electrode coupling reducing the capacitive effect. This behaviour is pronounced in the frequency below 10 GHz and strong for tungsten contacts. We explain the inductive response as a result of the interaction of stimulus current with the localized (or defects) states present at the contact region resulting in the current lagging behind the voltage. The results are further supported by direct current measurements that show tungsten to significantly increase carbon nanotube-electrode coupling. The immediate consequence is the reduction of the contact resistance, implying a reduction of electron tunnelling barrier from the electrode to the carbon nanotube.

Low-k Dielectric- A Potential Solution for Crosstalk Induced Signal Integrity issues in SWCNT Interconnects

Crosstalk creates signal integrity issues due to capacitive coupling between adjacent interconnect wires and it is a matter of concern in high frequency interconnects. The reported work on crosstalk induced signal integrity issues in CNT interconnects till date were assuming the value of coupling capacitance as equivalent to the coupling effect between metal interconnects of same dimensions. This work tries to fill that gap; by analyzing crosstalk in bundled SWCNTs with a better model for extracting inter bundle real life coupling capacitances. This work also proposes a novel idea of reducing crosstalk effects by using low-k dielectric materials as isolation between adjacent nets. It is found that compact bundles separated by low-k dielectric can reduce crosstalk effect considerably. Keywords - Crosstalk, signal integrity, SWCNT, MWCNT, Mixed CNT

Self-consistent design issues for high frequency Cu interconnect reliability incorporating skin effect

This paper presents a self-consistent method to guide high frequency reliability design for a two-level Cu interconnect structure, incorporating the impact of skin effect. A skin-effect-related parameter “Effective Cross Section Area” is introduced to make a more precise prediction of interconnects’ thermal profile due to self-heating. Since via and contact interfaces in Cu interconnects are at the highest risk of failure, via temperature is used to calculate the interconnect stress evolution and lifetime. From the research of the interconnect structure stressed by a type of arbitrary rectangular alternating current, we notice that the direction of the average current must be taken into account, while that consideration is not involved in self-consistent design for Al interconnects. We also found that generally, temperature, current density/intensity, frequency, and duty cycle are four specifications that restrict one another in high frequency interconnect reliability design, and if one increases, interconnects’ tolerance of the other three will decrease.

EFFECTS OF DC-BIAS CONDITIONS ON LOW-LOSS THIN FILM MICROSTRIP LINE

This paper presents the microwave characteristics of thin fllm microstrip line (TFML) under dc-bias conditions. The proposed TFML with 20m thick polyimide layer is used as a thin dielectric supporter on low-resistivity silicon (LRS) substrate. Measured frequency-dependent microwave characteristics and equivalent lumped elements are evaluated for the dc-biased TFML over 1{50GHz. This work presents acceptable attenuation of 0.561, 0.563 and 0.565dB/mm at 50GHz with dc-bias conditions, showing that the TFML can be used for high frequency interconnects for any 3D-based microwave devices and monolithic microwave integrated circuits (MMICs).

Design and Manufacturing of Stretchable High-Frequency Interconnects

The increasing number of biomedical applications for electronic systems have led to the need for stretchable electronics in order to significantly enhance the comfort of the user. This paper describes the design and manufacturing process of new stretchable high-frequency interconnects with meander-shaped conductors in a coplanar waveguide topology. The novel interconnects are produced based on laser-ablation of a copper foil, which is then embedded in a highly stretchable bio-compatible silicone material. Measurements on prototypes of the designed stretchable high-frequency interconnects revealed a maximal magnitude of -14 dB for the reflection coefficient and a minimal magnitude of -4 dB for the transmission coefficient in the frequency band up to 3 GHz. The influence of stretch on the performance of the high-frequency interconnects was analyzed using a stretch testing machine. The results showed that nor the magnitude, neither the phase of the transmission coefficient was influenced by elongations up to 20%.

A 8-GHz SiGe HBT VCO Design on a Low Resistive Silicon Substrate Using GSML

A practical layout method called ground shield microstrip lines (GSML) is investigated for the reliable design of high frequency interconnection lines on a low resistive silicon substrate. GSML facilitates the prediction of parasitic networks at the expense of introducing negligible loss. The microwave performance of a GSML line structure is compared to that of a conventional metal line on the same standard silicon substrate (20 Omegamiddotcm). Then, the GSML structure is applied to an 8-GHz SiGe heterojunction bipolar transistor (HBT) voltage-controlled oscillator (VCO) circuit. The GSML method replaces the post layout simulation and reduces iteration time, increasing design efficiency. A fully integrated differential tuning SiGe HBT 8-GHz VCO is designed and tested. The measured phase noise for the VCO is dBc/Hz at 1-MHz offset with an output power of dBm.

Characteristic impedance and signal loss measurements of head-to-preamplifier interconnects

The use of scattering parameters (S-parameters) to characterize high frequency interconnects has widely been used in the signal integrity field and is now being accepted into the disk drive arena as the preferred modeling tool for write and read path interconnects. The motivating factor for the shift from traditional lumped circuit models to S-parameter models has been the increase in data rates which exceed 1 GB/s. S-parameter models are convenient because they can be used directly in several high end spice circuit simulators as "black box" models. This paper will describe recent measurement techniques which make vector (VNA) network analyzer measurements possible for various interconnect structures up to 8.5 GHz. This paper will verify the results using time domain reflectometry (TDR) measurements of the same interconnect structures. Specific examples on signal losses, impedance, and coupling will be shown. Advances in achieving a broad range of differential impedances while maintaining high bandwidth will be demonstrated with idealized test structures.

Low-Loss and High-Frequency Interconnection Technology on Membrane Supported by Porous Silicon Post

A coplanar waveguide (CPW) has been fabricated on a 40 µm-thick porous silicon layer and the measured maximum available gain is -0.59 dB/mm at 40 GHz. The coplanar waveguide is then released in the air by etching the porous silicon layer under the signal line, which is supported at each end by porous silicon posts. The porous silicon post is surrounded by silicon sidewalls and a dielectric layer to protect it from the etchant. The porous silicon layer can be etched in 0.25 wt% NaOH solution with the rate of more than 2.5 µm/min but metal patterns are not attacked significantly by the etchant when there is no protection mask for them. A 5-mm-long coplanar waveguide has a maximum available gain of -1.32 dB at 40 GHz and a return loss of less than -16 dB up to 40 GHz. A maximum available gain of -0.2 dB/mm at 40 GHz is obtained when the gap between the membrane and silicon substrate is 100 µm. Because of its low-loss characteristic, the coplanar waveguide can be used for RF interconnection and multichip module package applications.

Pole-residue formulation for transient simulation of high-frequency interconnects using householder LS curve-fitting techniques

As digital circuits approach the GHz range, and as the need for high performance wireless devices increases, new simulation tools which accurately characterize high frequency interconnects are needed. In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented. The algorithm incorporates Householder LS curve-fitting techniques. The approach generates a universal macromodeling tool that enables simulation of interconnects in a modified version of simulation program with integrated circuit emphasis (SPICE). This results in a method that conveniently incorporates accurate EM models of interconnects or experimental data into a circuit simulator. The time domain simulation results using this new tool are compared with results from other simulators.

Modeling and metrology in high performance heat sink design

The evolution of the microprocessor has led to a significant increase in the number of I/O pads, the number of high frequency interconnects and power dissipation. The increase in performance has reduced board to board spacing, and as a result, the available space for thermal design in a computer system. High power dissipation and the small form factors have resulted in high density/high performance heat sinks. The current methods of measurement and modeling of heat sinks do not meet the accelerated product development cycles. This paper presents the modeling and metrology for requisite characterization of a heat sink and application of the data in a system computational fluid dynamics (CFD) model.

Hierarchical analysis of high frequency interconnect networks

Interconnect networks are analyzed using symbolic frequency domain analysis and an exact model of a distributed line. The analyzed network must have a tree structure and may contain transmission lines as well as other linear two-ports with specified transmission matrices. Any regular portion of the interconnect network is analyzed hierarchically with significant savings in analysis time. Numerical Laplace transform inversion is used to obtain time domain solutions. The event driven approach is adopted to reduce analysis time. Time complexity of the method depends on the regularity of the analyzed network, and can be as low as a logarithmic function of the number of elements for a hierarchically organized tree structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Characterization of high frequency interconnects using finite difference time domain and finite element methods

MIC and MMIC packages capable of good performance at frequencies as high as 60 GHz need to have small volume, low weight, microstrip and/or coplanar waveguide (CPW) compatibility and exhibit negligible electrical interference with the rest of the circuit. In order to acquire some of these characteristics, special provisions need to be made during circuit layout and design, resulting in high-density packages. The designed circuits have a large number of interconnects which are printed on electrically small surface areas and communicate through the substrate in a direct through-via fashion or electromagnetically through appropriately etched apertures. In a circuit environment of this complexity, parasitic effects such as radiation and cross talk are intensified, thus, making the vertical interconnection problem very critical. In this paper, transitions using through-substrate vias are considered and analyzed both in the time and frequency domains using the Finite Difference Time Domain (FDTD) technique and the Finite Element Method (FEM), respectively. The merits of each method in conjunction with accuracy, computational efficiency and versatility are discussed and results are compared showing excellent agreement. Specifically, a microstrip short-circuit, a microstrip ground pad, a CPW-to-microstrip through-via transition and a channelized CPW-to-microstrip transition are analyzed and their electrical performance is studied. >

Effect of Interfacial Characteristics of Metal Clad Polymeric Substrates on Electrical High Frequency Interconnection Performance

AbstractEtched metallic conductor lines on metal clad polymeric substrates are used for electronic component interconnections. Significant signal losses are observed for microstrip conductor lines used for interconnecting high Frequency (above 20 GHz) devices. At these frequencies, the electronic signal travels closer to the metal-polymer interface due to the skin effect. Copper-teflon interfaces were characterized by SEM and AES to determine the interfacial properties. Data relating roughness of the copper film to signal losses was compared to theory. Films used to enhance adhesion, were also found, to a lesser extent, to contribute to these losses.

A High Frequency Microcircuit Packaging and Interconnection System

The paper describes the development, characteristics, and application of a controlled impedance hermetic package (ClP) for microcircuit applications in microwave and fast-risetime pulse/digital domains. The primary motive is that of securing a significantly more economical packaging concept for high frequency microcircuits than is currently employed. Machined enclosures employing discrete coaxial connectors are currently widely used. A description is given of this planar package concept which is interfaceable with a strip transmission Iine motherboard. Pertinent electrical characteristics of the CIP including voltage standing wave ratio (VSWR) are presented. At this time, the upper limits of VSWR and frequency are 1.15 maximum at 5 gigahertz. The mechanical and physical characteristics, particularly the ability to secure reliable sealing and consequently hermetic-quality leak rates, are discussed. A description of CIP application methods including · microcircuit implanation, assembly, and-motherboard installation finalizes the presentation.