High-speed Encryption Research Articles

Ciphertext only attack on QR code optical encryption system with spatially incoherent illumination using a neural network

Abstract Optical encryption methods attract a lot of attention owing to their high encryption speed and bandwidth. Recently, neural networks (NNs) have been used for cryptanalysis of optical encryption techniques. In this paper, we for the first time to our knowledge applied a NN for ciphertext only attack on an optical encryption system with spatially incoherent illumination. A NN was used to extract encryption keys from ciphertexts, which can be used to decrypt the plaintext QR codes. Additionally, an optically encrypted QR code was successfully decoded after using the key extracted by the trained NN, that has been processed to account for discrepancies between the numerical model and the optical setup. The results show the vulnerability of the existing optical encryption system with incoherent light to attacks of this type, which indicates the need for improved optical encryption security.

High-Performance Implementation of a 1024-bit Full-Word Montgomery Modular Multiplier for High-Speed Encryption Hardware Circuit

High-Performance Implementation of a 1024-bit Full-Word Montgomery Modular Multiplier for High-Speed Encryption Hardware Circuit

On the Multilayer Planning of Filterless Optical Networks With OTN Encryption

With enhanced cost-effectiveness, filterless optical networks (FONs) have been considered as a promising candidate for future optical infrastructure. However, as the transmission in FON relies on the “select-and-broadcast” scenario, it is more vulnerable to eavesdropping. Therefore, encrypting the communications in FONs will be indispensable, and this can be realized by introducing the optical transport network (OTN) encryption technologies that leverage high-speed encryption cards (ECs) to protect the integrity of OTN payload frames. In this paper, we study the problem of security-aware multilayer planning of FONs with OTN encryption. We first formulate a mixed integer linear programming (MILP) model (i.e., w-MILP) to solve the problem exactly. Then, to reduce the time complexity of problem-solving, we transform w-MILP into two correlated MILP models for establishing fiber trees for an FON (t-MILP) and planning flows in the fiber trees (s-MILP), respectively. The optimization in t-MILP is further transformed into a weighted set partitioning problem, which can be solved time-efficiently. As for s-MILP, we propose a polynomial-time approximation algorithm based on linear programming (LP) relaxation and randomized rounding. Extensive simulations verify the performance of our proposals.

Use of implementations of arbitrary bitness permutations for cryptographic transformations

Background. Cryptographic transformations have always aroused the interest of the educated part of humanity and are an integral part of modern communications. A lot of different cryptographic algorithms exist for different tasks and requirements. Permutation functions are useful for cases where transformation speed is more critical than theoretical secrecy. Hardware implementation of such substitutions is quite simple.
 Objective. Investigate the model and combinational circuits for hardware implementation. Investigate algorithms for permutation functions software implementation. Investigate attack algorithms and cracking of permutation functions for cryptanalysis.
 Methods. The paper reviews algorithms of cryptographic transformations and their cryptanalysis for bijective permutations implemented by means of regular combinational structures of linear complexity. The proposed algorithms provide the rate of processing up to gigabits per second. The paper clarifies the algorithm of formation of elements of regular structures of permutations, specifies volumes of public and private data, reviews data formats, methods of their transfer and hardware implementation of one of the methods. The paper reviews attack types and permutation regular structure schemes cracking algorithms with experimental calculation of necessary operations quantity. The software implementation of the proposed algorithms for results calculation was developed.
 Results. Numerical results of the number of keys, the amount of memory required for hardware implementation and the number of required operations for cryptanalysis were obtained.
 Conclusions. The results show that the proposed algorithms for cryptographic transformations have a sufficient level of protection with a high-speed encryption and decryption.

Secure and Robust Internet of Things with High-Speed Implementation of PRESENT and GIFT Block Ciphers on GPU

With the advent of the Internet of Things (IoT) and cloud computing technologies, vast amounts of data are being created and communicated in IoT networks. Block ciphers are being used to protect these data from malicious attacks. Massive computation overheads introduced by bulk encryption using block ciphers can become a performance bottleneck of the server, requiring high throughput. As the need for high-speed encryption required for such communications has emerged, research is underway to utilize a graphics processor for encryption processing based on the high processing power of the GPU. Applying bit-slicing of lightweight ciphers was not covered in the previous implementation of lightweight ciphers on GPU architecture. In this paper, we implemented PRESENT and GIFT lightweight block ciphers GPU architectures. It minimizes the computation overhead caused by optimizing the algorithm by applying the bit-slicing technique. We performed practical analysis by testing practical use cases. We tested PRESENT-80, PRESENT-128, GIFT-64, and GIFT-128 block ciphers in RTX3060 platforms. The throughput of the exhaustive search are 553.932 Gbps, 529.952 Gbps, 583.859 Gbps, and 214.284 Gbps for PRESENT-80, PRESENT-128, GIFT-64, and GIFT-128, respectively. For the case of data encryption, it achieved 24.264 Gbps, 24.522 Gbps, 85.283 Gbps, and 10.723 Gbps for PRESENT-80, PRESENT-128, GIFT-64, and GIFT-128, respectively. Specifically, the proposed implementation of a PRESENT block cipher is approximately 4× higher performance than the latest work that implements PRESENT block cipher. Lastly, the proposed implementation of a GIFT block cipher on GPU is the first implementation for the server environment.

An Image Encryption Algorithm Based on an Epidemic Spreading Model

An intrinsic similarity was noted between epidemic spreading models and diffusion operations in cryptography. In this paper, a new image encryption algorithm is proposed based on an epidemic spreading model. The notable feature of the model is the evolution of the network node state. We utilize the evolution of an epidemic spreading model, namely the susceptible-infectious-recovered (SIR) model, to drive the encryption progress by abstracting pixels to the network nodes. In the new cryptosystem, the pixels in plain-text are considered as susceptible individuals, permutation and diffusion are seamlessly integrated rather than having two independent stages, and the encryptions are performed in a two-dimensional and nonlinear manner. Simulation results demonstrate its high encryption speed and excellent encryption security.

Multibiosignal chaotic encryption scheme based on spread spectrum and global diffusion process for e-health

E-health provides several remote health services highly convenient for patients. Nevertheless, inherent security risks are present in e-health such as data privacy since insecure communication channels are used to transmit data between patients and physicians or to cloud medical data storage. Nowadays, medical body area network provides a solution to continuous health monitoring with real-time updates of multibiosignal records in multiuser communication schemes for monitoring and early detection of medical conditions or diseases. In this paper, we propose to use chaos-based sequence direct spread spectrum technology and chaos-based cryptography to provide data privacy, high security and efficiency in monitoring multibiosignals in multiuser networks for e-health applications. First, each plain biosignal is modulated with sequence direct spread spectrum by using the chaotic Hénon map. Then, all modulated biosignals are summed to produce the modulated cryptogram. The modulated cryptogram is finally encrypted by using global diffusion process with the chaotic Hénon map to increase security by reducing the high autocorrelation of the modulated cryptogram. The experimental results are presented in a simulated multiuser scenario with 4 users (or patients) and 2 specialists (neurologist and cardiologist), with 12 biosignals acquired from database on the Internet, such as electroencephalograms, electromyograms, blood pressure signals, and electrocardiograms. A comprehensive security study is presented to show the high security, the high speed encryption, and the high noise interference robustness. According with the results, the proposed method can be used for secure multibiosignal monitoring in multiuser networks for e-health applications with high efficiency and security.

Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems

In this paper, we consider a schematic solution of the pipeline multiplier modulo, where multiplication begins with the analysis of the lowest order of the polynomial multiplier, which can serve as an operating unit for high-speed encryption and decryption of data by hardware implementation of cryptosystems based on a non-positional polynomial notation. The functional diagram of the pipeline and the structure of its logical blocks, as well as an example of performing the operation of multiplying polynomials modulo, are given. The correct functioning of the developed circuit was checked by modeling in the Vivado Design Suite computer-aided design for the implementation of the multiplication device on the development/evaluation kit Artix-7 based on the Spartan 6 field-programmable gate array series by Xilinx. The effectiveness of the proposed hardware pipeline multiplier in modulo is confirmed by the Verilog Testbench timing diagram implemented for the evaluation kit Artix-7 field-programmable gate array. In addition, the developed pipelined modulo multiplier takes no more than 0.02 % of the resources of the used field-programmable gate array for a given length of input data. Compared to the matrix multiplication method, a pipelined modulo multiplier can handle a large data stream without waiting for the result of the previous multiplication step. The modulo pipelined multiplier depth depends on the bit width of the input data. The developed pipeline device can be used in digital computing devices operating in a polynomial system of residue classes, as well as for high-speed data encryption in blocks of cipher processors operating on the basis of a non-positional polynomial number system.

Implementation of high speed and lightweight symmetric key encryption algorithm-based authentication protocol for resource constrained devices

Implementation of high speed and lightweight symmetric key encryption algorithm-based authentication protocol for resource constrained devices

Implementation of High Speed and Lightweight Symmetric Key Encryption algorithm Based Authentication Protocol for Resource-Constrained Devices

Implementation of High Speed and Lightweight Symmetric Key Encryption algorithm Based Authentication Protocol for Resource-Constrained Devices

Designing a New XTS-AES Parallel Optimization Implementation Technique for Fast File Encryption

XTS-AES is a disk encryption mode of operation that uses the block cipher AES. Several studies have been conducted to improve the encryption speed using XTS-AES according to the increasing disk size. Among them, there are researches on parallel encryption of XTS-AES using GPU. Although these studies focus on parallel encryption of AES, optimization for the entire XTS mode has not been performed. The reason is that the <inline-formula> <tex-math notation="LaTeX">$\alpha ^{j}$ </tex-math></inline-formula> computation process included in XTS mode is not suitable for parallel operation. Therefore, in this paper, we proposed several techniques for high-speed encryption in GPU by modifying XTS-AES into a form that is advantageous for parallel operation. The core idea is to pre-calculate the <inline-formula> <tex-math notation="LaTeX">$\alpha ^{j}$ </tex-math></inline-formula> calculation on the CPU into a form that is easy to operate on the GPU. To achieve this goal, we analyzed the <inline-formula> <tex-math notation="LaTeX">$\alpha ^{j}$ </tex-math></inline-formula> calculation process and present the parts that can be optimized. First, we presented a method that can replace multiple operations with a single table reference through the analyzed <inline-formula> <tex-math notation="LaTeX">$\alpha ^{j}$ </tex-math></inline-formula> computation progress. Thereafter, we proposed a method that can be calculated by partially skipping the entire <inline-formula> <tex-math notation="LaTeX">$\alpha ^{j}$ </tex-math></inline-formula> computation process that must be sequentially calculated through the table reference technique. For the proposed optimization implementation, we presented various results for evaluating the optimal implementation. In addition, we compared the performance of XTS-AES OpenSSL implementation on CPU and our proposed optimization implementation on GPU.

Implementation Method Of Remote Assistance Instruction Based On Hardware Secure Encryption

As a public service enterprise related to energy security and national economy and people’s livelihood, the safe work is related to all walks of life and thousands of households. In power scenarios, the remote cooperative guidance needs to ensure the security of data communication. The implementation method of remote cooperative guidance in power scenarios based on hardware security encryption realizes the functions of terminal registration, user online and offline management, message call, control signaling negotiation, audio and video real-time call, graphic guidance and target tracking and labeling. Configuration TF card encryption at the mobile terminal chip and video server configuration high speed encryption card, WIFI / 4 g wireless networks to establish encryption channel, remote collaborative guidance terminal power scene registration messages, messages, call, and by guiding and structured data security encryption transmission, the unstructured data such as audio stream and video stream is encrypted. It not only realizes the secure encryption of message communication, but also guarantees the high-speed transmission of audio and video streams.

Simulate the processing of data loss in sensor networks by proposing a high speed encryption mechanism

Prepare network sensor as a context to achieve network community everywhere , it has made&#x0D; technological innovations sensor smaller and more efficient to use in the discovery of the ocean and gain valuable&#x0D; information, it can be as simple as a temperature gauge or as complicated as if used in military and dangerous areas&#x0D; In order to transmit information safely and without any loss, it is necessary to study a dedicated processing&#x0D; mechanism for calculating the encryption taking into account the reduction of power consumption of the sensor node.&#x0D; the network has been simulated using QualNet

Security-Aware Planning of Packet-Over-Optical Networks in Consideration of OTN Encryption

The fast development of cloud computing and Big Data applications has promoted virtualization technologies such as network function virtualization (NFV), which in turn dramatically increased the amount of sensitive data being transmitted over the optical networks for datacenter interconnections (DCIs). To ensure the physical-layer security in DCIs, people have developed optical transport network (OTN) encryption technologies, i.e., leveraging high-speed encryption cards (ECs) to encrypt OTN payload frames. Although experimental studies have confirmed the benefits of ECs in terms of line-speed processing, low latency, and small encryption overhead, the problem of how to utilize them to build a secure packet-over-optical network with high cost-effectiveness has not been explored yet. In this paper, we study how to realize cost-effective and security-aware multilayer planning in a packet-over-optical network that covers both trusted and untrusted zones, in consideration of OTN encryption. We first formulate an integer linear programming (ILP) model to minimize the total capital expenditure (CAPEX) of the multilayer planning, which includes the costs of OTN linecards (LCs), ECs, and bandwidth resources, and solve the optimization exactly. Then, we prove the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NP</i> -hardness of the multilayer planning, and to reduce the time complexity, we propose a column generation (CG) model and design a more time-efficient approximation algorithm based on it. Our simulation results confirm the performance and advantages of our CG-based proposal, i.e., it is much more time-efficient than solving the ILP directly, and outperform the existing heuristic in terms of total CAPEX and costs of used LCs and ECs.

A selective encryption for H.264/AVC videos based on scrambling

H.264/Advanced Video Coding (H.264/AVC) is one of the video compression standards that is 50% more efficient than previously introduced standards. Given that the H.264/AVC standard is considered and used in a variety of video applications, it is essential to provide a suitable solution for video encryption with good security, high encryption speed, and to prevent bitrate increases. In this paper, we propose a method selective encryption of H.264/AVC for the digital rights management (DRM) applications. In this method, discrete cosine transform (DCT) coefficients, which affect the texture and content of the H.264/AVC video during compression, are encrypted after the zigzag scanning and based on Context-Adaptive Binary Arithmetic Coding (CABAC). The experimental results and encryption efficiency analysis demonstrate that the proposed method with the format compliance has good security and high encryption speed and it can prevent the bitrate from rising and is thus usable in industrial and the DRM applications.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

PurposeThe data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost.Design/methodology/approachThis work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture.FindingsThis paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications.Practical implicationsThe typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption.Social implicationsIt can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce.Originality/valueCompared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Cryptanalysis of an image block encryption algorithm based on chaotic maps

Recently, an image block encryption algorithm was proposed based on some well-known chaotic maps. The authors claim that the encryption algorithm achieves enough security level and high encryption speed at the same time. In this paper, we give a thorough security analysis on the algorithm from the perspective of modern cryptology and report some critical security defects on the algorithm. Given five chosen plain-images and the corresponding cipher-images, the attacker can obtain an equivalent secret key to successfully decrypt the other cipher-images encrypted with the same secret key. In addition, each security metric adopted in the security evaluation on the algorithm is questioned. The drawn lessons are generally applicable to many other image encryption algorithms.

EFFICIENT OPERATIONS IN LARGE FINITE FIELDS FOR ELLIPTIC CURVE CRYPTOGRAPHIC

An efficient method to compute the finite field multiplication for Elliptic Curve point multiplication at high speed encryption of the message is presented. The methods of the operations are based on dynamic lookup table and modified Horner rule method. The modified Horner rule method is not only to finite field operations but also to Elliptic curve scalar multiplication in the encryption and decryption. By comparison with using Russian Peasant method and in the new proposed method, one of the advantages of utilizing the proposed algorithm is that in the Elliptic Curve point addition are reduced by a factor of three in GF (2163). Therefore, using the Algorithm 1 running on Intel CPU, computation cost of the multiplication method is above 70% faster than using standard multiplication by Russian Peasant method. Ultimately, the proposed Algorithm 1 for evaluating multiplication can be made regular, simple and suitable for software implementations.&#x0D;

Chaos‐based privacy preserving vehicle safety protocol for 5G Connected Autonomous Vehicle networks

AbstractThere is a high demand for secure and reliable communications for Connected Autonomous Vehicles (CAVs) in the automotive industry. Privacy and security are key issues in CAVs, where network attacks can result in fatal accidents. The computational time, cost, and robustness of encryption algorithms are important factors in low latency 5G‐enabled secure CAV networks. The presented chaotic Tangent‐Delay Ellipse Reflecting Cavity‐Map system and PieceWise Linear Chaotic Map‐based encryption on short messages exchanged in a CAV network provide both robustness and high speed encryption. In this work, we propose a 5G radio network architecture, which leverages multiple radio access technologies and utilizes Cloud Radio Access Network functionalities for privacy preserved and secure CAV networks. The proposed Vehicular Safety Message identifier algorithm meets transmission requirements with a high probability of 85% for low round trip delay of ≤50 milliseconds. The proposed chaos‐based encryption algorithm exhibits faster speeds with a computational time of 2 to 3 milliseconds, showcasing its lightweight properties ideal for time critical applications.

A Guess-And-Determine Attack On SNOW-V Stream Cipher

Abstract The 5G mobile communication system is coming with a main objective, known also as IMT-2020, that intends to increase the current data rates up to several gigabits per second. To meet an accompanying demand of the super high-speed encryption, EIA and EEA algorithms face some challenges. The 3GPP standardization organization expects to increase the security level to 256-bit key length, and the international cryptographic field responds actively in cipher designs and standard applications. SNOW-V is such a proposal offered by the SNOW family design team, with a revision of the SNOW 3G architecture in terms of linear feedback shift register (LFSR) and finite state machine (FSM), where the LFSR part is new and operates eight times the speed of the FSM, consisting of two shift registers and each feeding into the other, and the FSM increases to three 128-bit registers and employs two instances of full AES encryption round function for update. It takes a 128-bit IV, employs 896-bit internal state and produces 128-bit keystream blocks. The result is competitive in pure software environment, making use of both AES-NI and AVX acceleration instructions. Thus, the security evaluation of SNOW-V is essential and urgent, since there is scarcely any definite security bound for it. In this paper, we propose a byte-based guess-and-determine attack on SNOW-V with complexity $2^{406}$ using only seven keystream blocks. We first improve the heuristic guessing-path auto-searching algorithm based on dynamic programming by adding initial guessing set, which is iteratively modified by sieving out the unnecessary guessing variables, in order to correct the guessing path according to the cipher structure and finally launch smaller guessing basis. For the specific design, we split all the computing units into bytes and rewrite all the internal operations correspondingly. We establish a backward-clock linear equation system according to the circular construction of the LFSR part. Then we further simplify the equations to adapt to the input requirements of the heuristic guessing-path auto-searching algorithm. Finally, the derived guessing path needs modification for the pre-simplification and post-reduction. This is the first complete guess-and-determine attack on SNOW-V as well as the first specific security evaluation to the full cipher.