HEVC Reference Model Research Articles

Quality Assessment of Dual-Parallel Edge Deblocking Filter Architecture for HEVC/H.265

Preserving the visual quality is a major constraint for any algorithm in image and video processing applications. AVC and HEVC are the extensively used video coding standards for various video processing applications in recent days. These coding standards use filters to preserve the visual quality of the processed video. To retain the quality of the reconstructed video, AVC uses an in-loop filter, called the deblocking filter, while HEVC uses two in-loop filters, the sampling adaptive offset filter and the deblocking filter. These filters are implemented in hardware by adopting various optimization techniques such as reduction of power utilization, reduction of algorithm complexity, and consuming lesser area. The quality of the reconstructed video should not be impacted by these optimization measures. For the HEVC/H.265 coding standard, a parallel edge deblocking filter architecture is designed, and the effectiveness of the parallel edge filter architecture is evaluated using various quantization values for various resolutions. The quality of the parallel edge filter architecture is on par with the HEVC reference model.

Analysis of coding unit partitioning and complexity reduction at intra-prediction mode of HEVC

ABSTRACT The emerging trend of ultra-high definition (4 K, UHD) video services necessitates coding efficiency, which is much higher than H.264. High-Efficiency Video Coding (HEVC) has been designed with the intention of drastically reducing the bit rate without compromising the video quality. The key feature is the introduction of a larger block structure with flexible block sizes from 64 × 64 to 8 × 8 samples. The enhanced feature has imposed higher complexity, specifically at the intra-prediction mode level of HEVC. The proposed research work has presented a novel hybrid approach to reducing the number of candidate Coding Units (CU) passing through irrelevant partition patterns and time-consuming iterative Rate-Distortion (RD) cost estimation process. The hybrid approach is implemented in two steps. In the first step gradient evaluation is performed and the CU is categorized as homogeneous or non-homogeneous. In the second step Early Termination is adopted by using machine learning for partitioning non-homogeneous CU. As the number of candidate Coding Units undergoing the time-consuming RD process is reduced by using the two-step hybrid approach, the proposed approach proves to be the best of its kind. The reduction in the number of candidate units undergoing the RD process reduces the complexity of the intra-prediction process. Encoding time is the measure of complexity and the proposed hybrid approach reduces the encoding time by an average of 36% compared with the HEVC reference model and also by an average of 26% as compared with the previous work. The Peak Signal to Noise Ratio (PSNR) reduced by an average of 0.1% indicates a slight reduction in the encoded image quality. The proposed approach significantly reduced the encoding time without affecting the RD performance of the encoder. The image quality is not compromised substantially when considering the improvement in the encoding time and the reduction in the complexity at an intra-prediction level.

Optimal Adaptive Quantization Based on Temporal Distortion Propagation Model for HEVC.

Optimal adaptive quantization is one of the key points to optimize the coding efficiency of video encoders. The latest block-based video compression standards, such as high-efficiency video coding (HEVC), extensively use predictive coding techniques that create dependencies between blocks and increase the complexity of optimal block quantizers search. Specifically, the motion compensation is responsible for a dependency network connecting all blocks of the same GOP together. In this paper, this dependency network is estimated by a temporal distortion propagation model and an accurate estimation of Inter and Skip modes probabilities. Optimal quantizers are then designed per block in order to achieve global optimization in terms of rate-distortion efficiency. By implementing the algorithm into the HEVC reference model (HM), we report -16.51% PSNR-based and -26.26% SSIM-based average bitrate savings compared to no adaptive quantization. The proposed algorithm outperforms several related methods from the state-of-the-art. Moreover, along with the demonstration of an optimal quantizer solution, we propose an in-depth analysis of the algorithm behavior. This analysis includes, among others, the relative distribution of rates between frames and the control of quantizers dynamic range.

Towards 3DoF+ 360 Video Streaming System for Immersive Media

Immersive video streaming has become very popular. To increase the quality of experience (QoE) with immersive media, user movement adaptive video streaming, three degrees of freedom plus (3DoF+), has emerged and is expected to meet this growing demand. Satisfying the limit of the bandwidth, providing high-quality immersive experience is challenging because 3DoF+ system requires high resolution, multi-view video transmission. This paper proposes a stride based 3DoF+ 360 video streaming system and introduces two main ideas: (i) a multi-view video redundancy removal method using view synthesis, (ii) a multi-view video residual packing method. The proposed multi-view video compression method removes redundancy between videos and packs them into one video, and it exhibits a BD-rate saving of 36.0% in maximum compared to the results of the high-efficiency video coding reference model. In addition, the proposed system requires fewer number of decoders for the clients, and it decreases the burden for immersive video streaming.

Robust real-time UHD video streaming system using scalable high efficiency video coding

With a new video coding standard high efficiency video coding (HEVC), the ultra high definition (UHD) TV service with robust video streaming technology is emerging in the TV industry. This paper addresses the system architecture for the UHD video streaming and proposes three main ideas: (i) picture prioritization method, (ii) error concealment mode signaling (ECMS), and (iii) Tile complexity-based parallel video processing. In the experiments using HEVC reference model conducted, the proposed picture prioritization method shows the gains in video quality from 2.2 to 7.5 dB in Y-PSNR, and the error concealment mode signaling gains from 0.2 to 2.5 dB in Y-PSNR, with corresponding subjective improvements. In addition, proposed parallel processing method for real-time decoding shows around 20% decoding speed up gain.

Fast Prediction Mode Decision in HEVC Using a Pseudo Rate-Distortion Based on Separated Encoding Structure

A novel fast algorithm is suggested for a coding unit (CU) mode decision using pseudo rate-distortion based on a separated encoding structure in High Efficiency Video Coding (HEVC). A conventional HEVC encoder requires a large computational time for a CU mode prediction because prediction and transformation procedures are applied to obtain a rate-distortion cost. Hence, for the practical application of HEVC encoding, it is necessary to significantly reduce the computational time of CU mode prediction. As described in this paper, under the proposed separated encoder structure, it is possible to decide the CU prediction mode without a full processing of the prediction and transformation to obtain a rate-distortion cost based on a suitable condition. Furthermore, to construct a suitable condition to improve the encoding speed, we employ a pseudo rate-distortion estimation based on a Hadamard transformation and a simple quantization. The experimental results show that the proposed method achieves a reduction in the total encoding time with a similar coding performance to that of the HEVC reference model.

Hardware Implementation and Performance Evaluation of the HEVC Intra-predicted $$4\times 4$$ 4 × 4 Blocks Transforms

This paper presents a performance evaluation of the high efficiency video coding (HEVC) based exclusively on the discrete cosine transform DCT-II and compares it to the reference algorithm which uses with the DCT-II, a discrete sine transform (DST-VI) for $$4\times 4$$4×4 intra-predicted luminance blocks. Then, a modified version of DST-VI called "MDST-VI" is proposed and evaluated. Using the HEVC reference model HM-16.3 and the main profile, the test results show that the MDST-VI presents an interesting compromise between the DST-VI and the DCT-II. The former leads to the best rate-distortion results, the latter yields a quality mean decrease of 0.02 dB and a mean bit-rate increase of 0.47 %, while the MDST_VI reduces the previous figures to the tenth. In a second part, a FPGA implementation performance analysis of the three transforms indicates that the DCT-II and the MDST-VI outperform the DST-VI with a 55.27 and 41.35 % area reduction, 47.73 and 10.61 % energy saving, and 85.70 and 10.55 % throughput gain, respectively. The MDST-VI could well fulfill the requirements of present and next-generation mobile communication where high-throughput and low-powered hardware accelerators are highly desirable while ensuring the best quality and the lowest bit-rate.

Redundancy Removal in Video frames using Luminance Masking

Digital video compression techniques have a crucial contribution in the world of telecommunication and multimedia sector where bandwidth is a valued constraint. A large amount of multimedia data has to be stored in a limited storage space. Hence, video compression techniques mainly focus on reducing the volume of information required for picture sequences/streaming pictures without losing much of its quality. Thus, in order to provide an competent compression method for multimedia data, Luminance Masking technique was proposed. In this context, an Intensity Dependant Spatial Quantization (IDSQ) perceptual means is proposed which attempts the intensity masking of the human visual system and perceptually adjusts quantization. IDSQ allows for adaptation to the video characteristics and its design meets low complication implementation requirements The proposed method has been incorporated into the HEVC reference model for the HEVC Range Extensions and its performance was judged by measuring the bit rate reduction against the HEVC Range Extensions.

Fast intra mode decision algorithm based on texture orientation detection in HEVC

The High Efficiency Video Coding is the new video coding standard, which obtains over 50% bit rate savings compared with H.264/AVC for the same perceptual quality. Intra-prediction coding in HEVC achieves high coding performance at the expense of high computational complexity, due to the high density of angular prediction modes, among other new features. This work presents a novel texture orientation detection algorithm by computing the local directional variance along a set of co-lines with rational slopes in the discrete lattice Λ. According with the dominant gradient detected, a reduced set of directional candidate modes is selected to be further checked by the rate-distortion optimization stage. The experimental results demonstrate the proposed algorithm can achieve a 30% computational complexity reduction compared with the HEVC reference model, with a negligible bit rate increase of 0.4%, and quality losses lower 0.03dB. Comparisons with similar state-of-the-art works show the proposed approach achieves the best trade-off between complexity reduction and rate-distortion.

High Dynamic Range Video Compression Exploiting Luminance Masking

The human visual system (HVS) exhibits nonlinear sensitivity to the distortions introduced by lossy image and video coding. This effect is due to the luminance masking, contrast masking, and spatial and temporal frequency masking characteristics of the HVS. This paper proposes a novel perception-based quantization to remove nonvisible information in high dynamic range (HDR) color pixels by exploiting luminance masking so that the performance of the High Efficiency Video Coding (HEVC) standard is improved for HDR content. A profile scaling based on a tone-mapping curve computed for each HDR frame is introduced. The quantization step is then perceptually tuned on a transform unit basis. The proposed method has been integrated into the HEVC reference model for the HEVC range extensions (HM-RExt), and its performance was assessed by measuring the bitrate reduction against the HM-RExt. The results indicate that the proposed method achieves significant bitrate savings, up to 42.2%, with an average of 12.8%, compared with HEVC at the same quality (based on HDR-visible difference predictor-2 and subjective evaluations).

Square-type-first inter-CU tree search algorithm for acceleration of HEVC encoder

In this paper, a fast inter-coding algorithm is proposed to reduce the computational load of HEVC encoders. The HEVC reference model (HM) employs the recursive depth-first-search (DFS) of the quad-tree search in terms of rate-distortion optimization in selecting the best coding modes for the best CU, PU, TU partitions, and many associated coding modes. The proposed algorithm evaluates the RD costs of the current CU only for its square-type PUs in the top-down search of the DFS. When the CU partition with the square-type PU is better than its sub-level CU partitions in terms of RD cost in bottom-up search of the DFS, the square type of current CU partition, along with its coding mode, is selected as the best partition. Otherwise, non-square-type PUs for the current CU level are evaluated. If the sub-partition is better than the CU with the non-square PUs, the sub-partition is finally selected as the optimum PU. Otherwise, the best non-square PU is selected as the best PU for the current level. Experimental results demonstrate that the proposed square-type-first inter-PU search can reduce the computational load in average encoding time by 66.7 % with 1---2 % BD loss over HM reference software. In addition, the proposed algorithm can yield an additional average time saving of 26.8---35.5 % against the three fast encoding algorithms adopted in HM.

Integer-Pel Motion Estimation for HEVC on Compute Unified Device Architecture (CUDA)

A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.

High Performance and FPGA Implementation of Scalable Video Encoder

A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.

Implementation of fast HEVC encoder based on SIMD and data-level parallelism

Abstract This paper presents several optimization algorithms for a High Efficiency Video Coding (HEVC) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of HEVC encoder, we found that interpolation filter, cost function, and transform take around 68% of the total computation, on average. In this paper, several software optimization techniques, including frame-level interpolation filter and SIMD implementation for those computationally intensive parts, are presented for a fast HEVC encoder. In addition, we propose a slice-level parallelization and its load-balancing algorithm on multi-core platforms from the estimated computational load of each slice during the encoding process. The encoding speed of the proposed parallelized HEVC encoder is accelerated by approximately ten times compared to the HEVC reference model (HM) software, with minimal loss of coding efficiency.

소프트웨어 기반 실시간 HEVC 인코더 구현을 위한 병렬화 기법에 관한 연구

ISO/IEC MPEG+ITU-T VCEG!,-./JCT-VC (Joint Collaborative Team on Video Coding)01)2 3HEVC (High Efficiency Video Coding)4H.264/AVC 567289:;!% ?@A1.1)0BCDE. FGH, IJK2L40MN OP<Q+RSKTUVW <XYZ[04\]^_`abc-.GKCdeE. HEVC  <XYZ2f g FhEidjkdlmn!bC de-o, djkdlm-.pqe4jZr%H-.HEVC  </stF 4uv!eE. wxay4R1)0z{|HEVC  <FhSIMD }~2!!€q) , CPU GPU2!‚ƒ„ † +‡:Ei  E. ˆ, !‰ nHEVC  KF ^KŠ ‹ ŒŽ5Fh E. w ybHM (HEVC reference model) 10.0K+832×480 ‘%<’“20~30fps<TUjZ2o”•-–, 1920×1080 ‘%<’“5~10fps<TUjZ2o”—DE.AbstractJoint Collaborative Team on Video Coding (JCT-VC), which have founded ISO/IEC MPEG and ITU-T VCEG, has standardized High Efficiency Video Coding (HEVC). Standardization of HEVC has started with purpose of twice or more coding performance compared to H.264/AVC. However, flexible and hierarchical coding block and recursive coding structure are problems to overcome of HEVC standard. Many fast encoding algorithms for reducing computational complexity of HEVC encoder have been proposed. However, it is hard to implement a real-time HEVC encoder only with those fast encoding algorithms. In this paper, for implementation of software-based real-time HEVC encoder, data-level parallelism using SIMD instructions and CPU/GPU multi-threading methods are proposed. And we also proposed appropriate operations and functional modules to apply the proposed methods on HM 10.0 software. Evaluation of the proposed methods implemented on HM 10.0 software showed 20-30fps for 832×480 sequences and 5-10fps for 1920×1080 sequences, respectively. Keyword : HEVC, encoder, real-time, parallelization˜#xa(Regular Paper)™,š›xaGb18œb6U, 201311ž(JBE Vol. 18, No. 6, November 2013)http://dx.doi.org/10.5909/JBE.2013.18.6.835ISSN 2287-9137 (Online) ISSN 1226-7953 (Print)