High Dielectric Constant Gate Insulator Research Articles

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

Incorporation of Al or Hf in atomic layer deposition TiO2 for ternary dielectric gate insulation of InAlN/GaN and AlGaN/GaN metal-insulator-semiconductor-heterojunction structure

This article investigates high dielectric constant gate insulators for GaN-based devices. Exploiting TiO2 as a high-κ insulator typically compromises leakage current and temperature stability of the film. In this work, the authors compare TiO2 mixed with either Al2O3 or HfO2 to form composite films Ti-Al-O and Ti-Hf-O, respectively, deposited by atomic layer deposition on both AlGaN/GaN and InAlN/GaN substrates. The authors investigated the compositional effects of the ternary compounds by varying the Al or Hf concentration, and the authors find that leakage current is reduced with increasing Al or Hf content in the film; with a maximum Al-content of 45%, leakage current is suppressed by about 2 orders of magnitude while for a maximum Hf-content of 31%, the leakage current is suppressed by more than 2 orders of magnitude compared to the reference TiO2 sample. Although the dielectric constant is reduced with increasing Al or Hf content, it is maintaining a high value down to 49, within the investigated com...

The Effect of Surface Energy on Atomic Layer Deposited Al2O3 Dielectric on MoS2 crystals

Molybdenum disulfide (MoS2) is a promising two-dimensional semiconductor for thin-film transistors (TFTs) because of the high field-effect mobility, low subthreshold swing, and high on/off ratio. For the fabrication of high-performance MoS2 TFTs, it is essential to integrate a high dielectric constant (high-k) gate insulator such as HfO2 or Al2O3 on MoS2. However, the absence of dangling bonds or functional groups on MoS2 basal plane often requires the pretreatment of MoS2 surface by O2 plasma or ultraviolet (UV)-O3, which will inevitably influence the surface energy. In this presentation, we report a systematic investigation on the effect of MoS2 surface energy on the atomic layer deposited (ALD) Al2O3. We correlate the surface coverage and morphology of ALD Al2O3 dielectric with the MoS2 surface energy based on the measurement with scanning electron microscopy (SEM), atomic force microscopy (AFM), x-ray photoelectron spectroscopy (XPS), and Raman spectroscopy. We also provide electrical properties of functionalized Al2O3/MoS2 interface with current-voltage (I-V) and capacitance-voltage (C-V) characteristics.

ZnO TFTs prepared by chemical bath deposition technique with high‐k La2O3 gate dielectric annealed in ambient atmosphere

In this paper, the electrical properties of top‐gated thin‐film transistors with low‐cost chemical bath deposition (CBD) of ZnO as active material and a high‐k rare‐earth oxide La2O3 as gate dielectric have been reported. The source‐drain and gate electrodes and dielectric layers are fabricated by thermal evaporation techniques in high vacuum of the order of 10−6 Torr in a coplanar electrode structure. The channel length of the TFT is of 50 μm. The fabricated TFTs are annealed at 500 °C in air. The TFTs exhibit a field effect mobility 0.58 (cm2 V−1 s−1). Use of a high dielectric constant (high‐k) gate insulator reduces the threshold voltage and subthreshold swing of the TFTs. The TFTs exhibit a low threshold voltage of 4 V. The calculated values of gain–bandwidth product and subthreshold swing are also evaluated and presented. The ON/OFF ratio of the TFT is found to be 106.

Growth and characterization of sol–gel prepared Gd2O3 films as gate insulators for Zn–Sn–O thin film transistors

A solution-processed oxide thin film transistor (TFT) with low operating voltage is demonstrated using a high dielectric constant Gd2O3 gate insulator. Prepared using spin coating followed by annealing at 400°C, the Gd2O3 film exhibits a dielectric constant in the range of 10–12 with a breakdown field as high as 3.5MVcm−1. A proper amount of polymeric agent, polyvinylpyrrolidone (PVP), is very important to access uniform film growth, a smooth surface morphology, and a low leakage current, while the annealing temperature and film thicknesses are important as well for the operational solution-processed gate insulator. The resultant Zn–Sn–O/Gd2O3 TFT exhibits enhanced performance with a field-effect mobility of ~2.53cm2V−1s−1 by a factor of 8.7 compared with the TFTs using a SiO2 insulator with an exceptionally low operating voltage<10V.

Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with High-k Dielectric Nd2O3. Use of high dielectric constant (high-k) gate insulator Nd2O3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 × 104 and mobility is 0.13cm2/V.s. Pentacene film is deposited on Nd2O3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature.

Projected performance advantage of multilayer graphene nanoribbons as a transistor channel material

The performance limits of a multilayer graphene nanoribbon (GNR) field-effect transistor (FET) are assessed and compared with those of a monolayer GNRFET and a carbon nanotube (CNT) FET. The results show that with a thin high dielectric constant (high-κ) gate insulator and reduced interlayer coupling, a multilayer GNRFET can significantly outperform its CNT counterpart with a similar gate and bandgap in terms of the ballistic on-current. In the presence of optical phonon scattering, which has a short mean free path in the graphene-derived nanostructures, the advantage of the multilayer GNRFET is even more significant. Simulation results indicate that multilayer GNRs with incommensurate non-AB stacking and weak interlayer coupling are the best candidates for high-performance GNRFETs.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2∕Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

High performance flexible pentacene thin-film transistors fabricated on titanium silicon oxide gate dielectrics

Pentacene thin-film transistors (TFTs) with a high dielectric constant gate insulator, titanium silicon oxide (TiSiO2), were fabricated on flexible polyethylene naphthalate films coated with indium tin oxide layers. In order to define the device characteristics, the thickness dependence of the gate dielectric properties was studied. The pentacene TFT with a 132-nm-thick TiSiO2 film showed high performance with a threshold voltage of −0.88V, an inverse subthreshold slope of 317mV/decade. From the current-voltage characteristics, the field-effect mobility was obtained, resulting in an impressive mobility of 0.67cm2∕Vs at an operating voltage as low as −5V.

Polymer thin-film transistor based on a high dielectric constant gate insulator

In this paper full polymer thin-film transistors (PTFTs) based on Poly (acrylonitrile) (PAN) as the gate dielectric and poly (2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylene-vinylene) (MEH-PPV) as the semiconductor layer were investigated by using different channel width/length ratios. Relatively high dielectric constant of the polymer dielectric layer (6.27) can remarkably reduce the threshold voltage of the transistors to below -3?V. Hole field-effect mobility of MEH-PPV of the PTFTs was about 4.8?10?4cm2/Vs, and on/off current ratio was larger than 102, which was comparable with that of transistors with widely used Poly (4-vinyl phenol) (PVP) or SiO2 as gate dielectrics.

High-performance pentacene thin-film transistors with high dielectric constant gate insulators

Pentacene thin-film transistors (TFTs) with titanium silicon oxide (Ti1−xSixO2) gate insulator have been fabricated to realize high field-effect mobility at practical voltages. The Ti1−xSixO2 films deposited by rf sputtering exhibited a flat surface and high dielectric constant. The pentacene TFT with the Ti1−xSixO2 gate insulator had high performance with a threshold voltage of −1.6V, an inverse subthreshold slope of 0.13V∕decade, and a current on/off ratio of 107 at a voltage of −10V. The field-effect mobilities of higher than 1cm2∕Vs were obtained in the whole voltage range of −2to−15V.

Active Matrix Driving Organic Light-Emitting Diode Panel Using Organic Thin-Film Transistors

We developed an active matrix driving organic light-emitting diode (OLED) panel on a glass substrate using two organic thin-film transistors (OTFTs) per pixel, a switching OTFT and a driving OTFT. The OTFTs are bottom contact structures with the high-dielectric constant gate insulator tantalum oxide (Ta2O5, relative dielectric constant of 23) produced by anodization in ammonium adipate solution and with pentacene as the active layer. The W/L (where W and L are the OTFTs channel width and length, respectively) was 400 µm/10 µm for the switching OTFTs and 680 µm/10 µm for the driving OTFTs. The characteristics of the OTFTs were improved by treating the Ta2O5 surface with hexamethyldisilazane (HMDS), so that the field-effect mobility was 2.0×10-1 cm2 V-1 s-1 and the current on/off ratio was 105. A green phosphorescent dopant, tris(2-phenylpyridine)iridium [Ir(ppy)3], was used for the OLED layer. The panel had 8×8 pixels and the aperture ratio was 27%. We confirmed a 16-gray-scale representation and a luminance of 400 cd/m2.

Poly(3-hexylthiophene) field-effect transistors with high dielectric constant gate insulator

High dielectric constant (k=41) titanium oxide (TiO2) was used as the gate insulator in field-effect transistors (FETs) with regioregular poly(3-hexylthiophene) (RR-P3HT) as the electronically active semiconductor. Good FET characteristics were obtained with saturation at low drive voltages (≈−2 V) and with carrier mobilities of 1.3×10−2 cm2/V s. Deposition of a thin layer of SiO2 (thicknesses of 3 and 17 nm) on top of the TiO2 (97 nm) gate insulator resulted in a reduced effective dielectric constant (keff=31 for 3 nm of SiO2 and keff=19 for 17 nm SiO2), but with significant improvement in the FET characteristics; the field-effect mobility increased to 5.4×10−2 cm2/V s, the on/off ratio increased from 102 to 6×104, and the leakage current decreased by a factor of approximately 102. The importance of the thin SiO2 layer was confirmed using aluminum oxide (Al2O3) (k=8.4) as the gate insulator in RR-P3HT FETs.

Behavior of hydrogen in high dielectric constant oxide gate insulators

Interstitial hydrogen is calculated to act as a shallow donor in the candidate high dielectric constant (k) gate oxides ZrO2, HfO2, La2O3, Y2O3, TiO2, SrTiO3, and LaAlO3 but is deep in the oxides SiO2, Al2O3, ZrSiO4, HfSiO4, and SrZrO3. This may account for the change of sign of fixed charge in oxides, from negative in Al2O3 to positive in HfO2.

Polymer thin-film transistors with high dielectric constant gate insulators

Field-effect transistors consisting of poly(3-hexylthiophene) have been fabricated with high dielectric constant SrBi2Ta2O9 films working as the gate insulator. Significantly enhanced gate effects were observed in these devices compared to similar transistors with conventional SiO2 gate dielectric. Our devices exhibited operating voltages around 10 V, as compared to about 100 V for devices employing SiO2 as the gate dielectric. Moreover, inverters based on such polymer transistors were demonstrated with nice input–output characteristics.

Electron energy-loss spectroscopy analysis of interface structure of yttrium oxide gate dielectrics on silicon

Interface stability of high dielectric constant gate insulators on silicon is an important issue for advanced gate stack engineering. In this article, we analyze the silicon/dielectric interface structure for thin Y2O3 and Y silicate films deposited by chemical vapor deposition on clean and prenitrided Si(100) using high-resolution transmission electron microscopy, electron energy-loss spectroscopy, and x-ray photoelectron spectroscopy. The analysis shows the films to be stoichiometric Y2O3 on top and Y-silicate/SiO2 at the dielectric/Si interface. Prenitridation of the silicon surface impedes the reaction between the depositing film and the substrate, promoting a Si-free Y2O3 structure. Possible mechanisms leading to the observed Y2O3 and Y silicate structures are discussed.

Advances in high-k dielectric gate materials for future ULSI devices

This article discusses recent developments in high dielectric constant gate insulator materials for future ultra-large-scale integration devices below 100 nm. Since conventional gate oxide poses problems as device features are scaled down, it becomes necessary to develop new gate dielectric materials with properties similar to SiO2 and compatible with current complementary metal-oxide semiconductor technology. As the thickness of silicon dioxide approaches less than 1.5 nm, the leakage current becomes higher than 1 A/cm2 and tunnel current increases significantly. Therefore, materials are needed to provide excellent electrical characteristics such as dielectric constant higher than 30, interface-state-density less than 1 × 1011/cm2-eV, tunneling current less than 10 mA/cm2, and negligible hysteresis. Many high dielectric constant materials have been reported that could potentially replace SiO2. These include SiOxNy, Ta2O5, TiO2, Y2O3, CeO2, SrTiO3, Al2O3, La2O3, and silicates of hafnium and zirconium. These materials exhibit the desired high dielectric constants for applications as gate dielectrics in sub-100 nm silicon technology. However, detailed studies need to be performed to evaluate the compatibility of these materials with the rest of the silicon integrated-circuit manufacturing processes.

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.