High Density SRAM Cell Research Articles

Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells

In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VTH compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations.

Проектирование топологии сбоеустойчивых ячеек статической памяти высокой плотности

Проектирование топологии сбоеустойчивых ячеек статической памяти высокой плотности

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

Numerical simulation of hard errors induced by heavy ions in 4T high density SRAM cells

2D numerical simulation of local dose deposition effects in N channel MOS transistors are presented in order to explain experimental observation of stuck bits in 4 T resistor loaded cells of high density SRAMs irradiated by heavy ions. The ion impact location in the channel is shown to strongly modulate the observed threshold voltage shift. This shift variation versus the inverse channel length is super linear, so more important effects are expected for 4T cells as transistor dimensions are reduced. >