High Data Processing Rate Research Articles

Design of Eight Parallel 512-Point MDF FFT/IFFT Processor for WPAN Applications

This paper presents a high-speed FFT algorithm for high data rate wireless personal area network applications. In a wireless personal area network, the FFT/IFFT block leads the major role. Computational requirements of FFT processors are a heavy burden in most real-time applications. From the previous work, it can be recognized that most of the FFT structures follow the divide and conquer algorithms, which improve the computational efficiency. In the proposed model, a new design of 512-point FFT/IFFT processor is derived by mixed approach for a Radix-26 algorithm, which has been presented and implemented using the Eight Parallel Multipath Delay Feedback (MDF) architecture. In this work, three distinct complex multiplication approaches are derived; from the analysis, a mixed approach has been proposed to reduce the multiplier complexity and also the equivalent normalized area. The proposed design is compiled and simulated with 90[Formula: see text]nm CMOS technology optimized for a 1.2[Formula: see text]V supply voltage. The proposed Mixed Radix-26 algorithm has been verified and validated using existing architectures. It has been found that the proposed mixed approach for Radix-26 algorithm reduces the normalized area by 8.603% compared with verified architectures. Also, the multiplier complexity is reduced by more than 33% using Canonical Signed Digit constant multiplier. The proposed architecture is suitable for applications like OFDM based WPAN applications at high data processing rates.

Hardware Development of Electrical Capacitance Tomography (ECT) System with Capacitance Sensor for Liquid Measurements

Electrical capacitance tomography system is useful for obtaining information about the spatial distribution of a mixture of dielectric materials inside a vessel. This research aims to obtain real-time monitoring on the composition for liquid mixture in conveying pipeline. ECT is a non-invasive, non-intrusive and non-destructive technique that can measure the flow level inside a pipeline. In order to increase the image resolution and accuracy of current tomography research, a study on 16 electrodes sensor ECT system has been developed. The developed system has the flexibility to be assembled and moved from a pipeline to another. The intelligent on-board flexibility and mobility sensor technique is a new technique for ECT system. The system can be assembled in different diameter sizes of pipeline, and numbers of electrodes sensor can be reduced accordingly depending on the pipeline sizes without the need to redesign the electrodes sensor. The new design is equipped with high speed data processing rate data acquisition system and high speed data reconstruction. A microcontroller that support full-speed USB data transfer rate has been designed as the centralization control unit. In order to improve data result, iterative algorithm has been implemented in this system in order to obtain a precise image of the flow in the pipeline. As a result, the ECT system is able to reconstruct various multiphase flow images.

Architecture and Performance of the Hardware Accelerators in IBM’s PowerEN Processor

Computation at the edge of a datacenter has unique characteristics. It deals with streaming data from multiple sources, going to multiple destinations, often requiring repeated application of one or more of several standard algorithmic kernels. These kernels, related to encryption, compression, XML Parsing and regular expression searching on the data, demand a high data processing rate and power efficiency. This suggests the use of hardware acceleration for key functions. However, robust general purpose processing support is necessary to orchestrate the flow of data between accelerators, as well as perform tasks that are not suited to acceleration. Further, these accelerators must be tightly integrated with the general purpose computation in order to keep invocation overhead and latency low. The accelerators must be easy for software to use, and the system must be flexible enough to support evolving networking standards.In this article, we describe and evaluate the architecture of IBM’s PowerEN processor, with a focus on PowerEN’s architectural enhancements and its on-chip hardware accelerators.PowerEN unites the throughput of application-specific accelerators with the programmability of general purpose cores on a single coherent memory architecture. Hardware acceleration improves throughput by orders of magnitude in some cases compared to equivalent computation on the general purpose cores. By offloading work to the accelerators, general purpose cores are freed to simultaneously work on computation less suited to acceleration.

A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is 0.93 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation.

High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems

This paper presents a high-throughput low-complexity four-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. Four-parallel processing is used to achieve 12-Gbps data throughput and low hardware complexity. Also, the proposed pipelined folded Degree-Computationless Modified Euclidean (fDCME) algorithm is used to implement the key equation solver (KES) block, which provides low hardware complexity for the RS decoder. The proposed four-parallel RS decoder is implemented 90-nm CMOS technology optimized for a 1.2V supply voltage. The implementation result shows that the proposed RS decoder can be operated at a clock frequency of 400MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity. Therefore it can be applied in the FEC devices for next-generation high-rate WPAN systems with data rate of 10-Gbps and beyond.

A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (Dual-pSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. Two-parallel processing allows the decoder to achieve a high data processing rate required for 100 Gb/s optical communication systems. Also, the proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10?15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.

Optimum estimate of delays and dispersive effects in low-frequency interferometric observations

<i>Context. <i/>Modern radio interferometers sensitive to low frequencies will make use of wide-band detectors (with bandwidths of the order of the observing frequency) and correlators with high data processing rates. It will be possible to simultaneously correlate data from many sub-bands spread through the whole bandwidth of the detectors. For such wide bandwidths, dispersive effects from the atmosphere introduce variations in the fringe delay which change through the whole band of the receivers. These undesired dispersive effects must be estimated and calibrated with the highest precision.<i>Aims. <i/>We studied the achievable precision in the estimate of the ionospheric dispersion and the dynamic range of the correlated fringes for different distributions of sub-bands in low-frequency and wide-band interferometric observations. Our study is focused on the case of sub-bands with a bandwidth much narrower than that of the total covered spectrum (case of LOFAR).<i>Methods. <i/>We computed the formal statistical uncertainty of the ionospheric delay, the delay ambiguity and the dynamic range of the correlated fringes using four different kinds of distributions of the sub-bands: constant spacing between sub-bands, random spacings, spacings based on a power-law distribution, and spacings based on Golomb rulers (sets of integers, <i>n<i/><sub><i>i<i/><sub/>, whose sets of differences, <i>n<i/><sub><i>j<i/><sub/> – <i>n<i/><sub><i>i<i/><sub/>, have non-repeated elements).<i>Results. <i/>We compare the formal uncertainties in the estimate of ionospheric effects in the data, the ambiguity of the delays, and the dynamic range of the correlated fringes for the four different kinds of sub-band distributions.<i>Conclusions. <i/>For a large number of sub-bands (>20, depending on the delay window) spacings based on Golomb rulers give the most precise estimates of dispersive effects and the highest dynamic ranges of the fringes. Spacings based on the power-law distribution give similar (but slightly worse) results, although the results are better than those from the Golomb rulers for a smaller numbers of sub-bands. Random distributions of sub-bands result in relatively large dynamic ranges of the fringes, but the estimate of dispersive effects through the band is worse. A constant spacing of sub-bands results in very bad dynamic ranges of the fringes, but the estimates of dispersive effects have a precision similar to that obtained with the power-law distribution. Combining all the results, the power-law distribution gives the best compromise between homogeneity in the sampling of the bandwidth, precision in the estimate of the ionospheric dispersive effects, dynamic range of the correlated fringes, and ambiguity of the group delay.

Pipelined recursive modified Euclidean algorithm block for low-complexity, high-speed Reed–Solomon decoder

A novel pipelined recursive modified Euclidean (ME) algorithm block for the low-complexity, high-speed Reed–Solomon (RS) decoder is presented. The deeply pipelined recursive structure enables implementation of a significantly low-complexity ME algorithm block with much improved clock frequency. The low-complexity, high-speed RS decoder using the pipelined recursive ME algorithm block has been implemented in 0.13 µm CMOS technology with a supply voltage of 1.1 V. The results show that it has significantly low hardware complexity and a high data processing rate of 6.16 Gbit/s.

Use of a photothermoplastic disk for storing two-dimensional Fourier holograms in optical data-processing systems

The fundamental principles of locally recording two-dimensional holograms on a photothermoplastic disk by heating with an infrared laser are considered. The method developed was used in making a holographic photothermoplastic disk with homogeneous storage characteristics. The promising aspects of designing a system based on a holographic photothermoplastic disk and using the parallel data-processing principle, such as an optical neural network and an optical correlator, are pointed out. The principle merit of these systems is their high data-processing rate with a large storage capacity for standard patterns. The possibilities are indicated of implementing low-frequency spatial image filtering by recording matched niters and holograms, of recording complex filters by superposition, and of local rerecording of data on a photothermoplastic disk.

High‐altitude resolution stratospheric measurements with the Arecibo 430‐MHz radar

The potential of the Arecibo 430‐MHz radar for the study of stratospheric dynamics and turbulence has been recently established. In the past the instrumented resolution of the system has been larger than 300–600 m. The present paper describes instrumental modifications which have enabled us to obtain a resolution of 150 m, the maximum allowed by the transmitter bandwidth. Such a gain in resolution is very important for stratospheric studies, since it is expected that turbulence occurs at these altitudes in layers with thickness between a few tens to a few hundred meters. Furthermore, a complementary coded pulse scheme has been used for the first time. Such a code has the advantage of generating no pulse side lobes, an important property for defining the quiet regions existing in between turbulent layers. Decoding is performed digitally. The high data processing rate is taken care of by the use of a preprocessor. Power spectra of the signals corresponding to 256 altitudes are evaluated on line by means of an array processor peripheral connected to the processing computer. Useful echoes have been obtained from 10 km to about 30 km. The existence of layers of turbulence has been demonstrated, and their separation has been determined, but the thickness of some of them has still not been fully resolved. The separation of the layers varies as a function of altitude, changing from a few hundred meters at lower stratospheric heights to a few kilometers at 25‐ to 30‐km altitudes. The results obtained show the importance of high resolution when using radars to obtain wind information from the Doppler shift of turbulence echoes.

Organization of No. 1 ESS Central Processor

The central processor controls the operation of the No. 1 electronic switching system by executing sequences of program instructions. The logical organization of the central processor is described by the simultaneous evolution of: (1) an instruction repertoire to carry out the required telephone and system maintenance tasks efficiently, and (2) a circuit logic design to provide the necessary circuits (flip-flop registers, accumulators, etc.) to execute the instructions at a high data processing rate. The design aims, order structure, timing, internal sequencing, and communications with the peripheral equipment of the system are described.