High-current Phenomena Research Articles

Preface to Special Issue on New Development of Numerical Simulation Technology of High Current Phenomena

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New Development of Numerical Simulation Technology of High Current Phenomena

New Development of Numerical Simulation Technology of High Current Phenomena

An Investigation of DC and RF Safe Operating Area of n-p-n $+$ p-n-p SiGe HBTs on SOI

We have examined the reliability risks of complementary SiGe HBTs on thick-film silicon on insulator (SOI). DC stress techniques, such as reverse emitter-base (EB) stress, mixed-mode stress, and flyback measurements, were used to characterize the safe operating area of n-p-n and p-n-p SiGe HBTs fabricated on SOI substrates. The measurements were analyzed based on fundamental damage mechanisms, such as hot carriers generated at the EB and collector-base junctions during large reverse voltage, and thermal runaway as a result of high current phenomena. RF stress (using a large amplitude continuous-wave signal) was also performed to examine the reliability of complementary bipolar complementary metal-oxide-semiconductor devices and circuits in an RF context. In both cases, p-n-p SiGe HBTs were found to be more reliable than n-p-n SiGe HBTs, a fact that may offer opportunities for circuit design optimization.

Catastrophic Failure in Highly Scaled Commercial NAND Flash Memories

Heavy ion single-event measurements on a variety of high density commercial NAND flash memories are reported. Three single event effect (SEE) phenomena were investigated: single effect upsets (SEUs), single effect functional interrupts (SEFIs), and a new high current phenomenon which at high LETs results in catastrophic loss of ability to erase and program the device.

Single Event Effect Characterization of High Density Commercial NAND and NOR Nonvolatile Flash Memories

Heavy ion single-event measurements on a variety of high density commercial NAND and NOR flash memories were reported. Three SEE phenomena were investigated: SEUs, SEFIs, and catastrophic loss of ability to erase and write to the device. Although for all devices under test SEUs and SEFIs were observed, these commercial high densities devices appear to be much less susceptible than typical flash devices that have been tested lately. A new high current phenomenon in the high density NAND flash memories and charge pump failure in the NOR flash memory are discussed.

Analytical base-collector heterojunction capacitance model including collector current effects

The base-collector heterojunction space-charge-region capacitance of double heterojunction bipolar transistors is treated. This capacitance cannot be modeled as the conventional heterojunction depletion capacitance because it is heavily influenced by the collector current, which is neglected in the depletion capacitance model. The analysis includes heterojunction effects as well as high current phenomena such as base pushout and space-charge-limited flow. Large discrepancies are found when comparing the present model with the depletion model at high current densities. Comparison of the base-collector junction capacitances calculated from a single heterojunction bipolar transistor and a double heterojunction bipolar transistor is also included.