High Common Mode Rejection Ratio Research Articles

A chopper amplifier with adaptive biasing OTA for biomedical applications, featuring high gain and CMRR.

This paper presents a design of fully differential chopper amplifier employing the flipped voltage follower (FVF) adaptive biasing technique, focusing on its potential use in biopotential recording applications. The suggested architectural OTA incorporates self-cascoded current mirrors (SCCMs) as the active load to achieve a substantial output swing. The FVFs based adaptive biasing approach for the differential input stage boosts extra current and enhances gain and dynamic characteristics. The chopper amplifier attains a common mode rejection ratio (CMRR) of more than 100 dB through the strategic utilization of chopper modulators and pseudo-resistors. Additionally, this device exhibits characteristics such as accurate and stable gain, high input impedance, and a compact physical footprint. The present study also includes a comparison between the suggested structure and the bio-potential amplifiers discussed in the existing literature. This comparison is based on key metrics such as gain, input referred noise (IRN), CMRR, and input impedance (Zin). The proposed structure yielded a gain of 63.72 dB, an IRN of 0.07nVrms, a CMRR of 127.97 dB and a Zin of 1.54 GΩ. The bio-potential chopper amplifier under consideration was constructed and simulations were performed by utilizing the Cadence Virtuoso Spectre simulator tool at 180 nm CMOS technology node.

Reconfigurable Low-Power CMOS Amplifier Stages for Broadband Impedance Spectroscopy

In this paper, a fully differential amplifier is proposed in a 1.8 V-0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology, which can accommodate both voltage (V-mode) and current (C-mode) inputs. Post-layout simulation results show a fixed gain amplifier exhibiting a 26 dB (V-mode)/89 dBΩ (C-mode) gain and a programmable gain amplifier featuring a 6–26 dB gain, overall yielding a 26.8–46.4 dB dB (V-mode)/89.6–109.2 dBΩ (C-mode) programmable gain range, with a 100 MHz bandwidth and a power and area consumption of 360.5 µW and 0.0177 mm2, respectively. This amplifier has been designed considering the constraints and specifications (including low voltage, low power, reduced noise and high common mode rejection ratio) for its use in an analogue Lock-in-based Frequency Response Analyser-Impedance Spectroscopy (FRA-IS) device. The proposed design introduces a novel fully differential open-loop structure based on a transconductance–transimpedance (TC-TI) topology for high performance applications with a broad programmable bandwidth. To compare this work, different figures of merit (FoMs) are introduced as well as a comparison table with other simulated and experimental results, reporting an overall better performance in terms of gain, frequency and power-area consumption.

A Compact Model for Carbon Nanotube Field Effect Transistors Incorporating Temperature Effects and Application for Operational Amplifier Design

Semiconducting carbon nanotubes (CNTs), characterized by high carrier mobility and atomic thickness, are considered ideal channel materials for building high-performance and ultimate-scale field-effect transistors for future electronics. Here, we present a data-calibrated compact model of CNT field-effect transistors (CNTFETs) that incorporates temperature effects using the virtual source approach. The proposed model also includes the self-heating effect. Temperature effect was characterized by the influence of temperature on devices, achieved through establishing a temperature-dependent semi-empirical model of carrier mobility and carrier velocity. The proposed model can be easily implemented in a simulator. We designed a two-stage operational amplifier (OPAMP) using the proposed model at 32 nm technology. Compared with other studies, the designed CNTFET-based OPAMP demonstrates lower power consumption, which is beneficial for exploring the biological applications of low-power analog circuits in portable electronic devices. Furthermore, the impact of thermal variations on the design of OPAMP, as per the proposed model, was delineated. Investigations revealed that our circuit maintains a high common mode rejection ratio, which diminishes as the temperature increases and exhibits a moderate gain value that escalates with temperature.

A Rail-to-Rail Operational Amplifier for Transimpedance Optoelectronic Conversion

The transimpedance conversion circuit is an important part of the fluorescent optical fiber temperature sensor, which is used for rare earth fluorescence detection. Transimpedance conversion circuits can benefit from the wide input range, high gain, low input offset voltage, and high common-mode rejection ratio of rail-to-rail operational amplifiers. In this paper, a constant transconductance rail-to-rail operational amplifier is designed and implemented based on the 0.18 μm CMOS process. According to the simulation results, the transconductance change rate of the operational amplifier is 4.8%, and its gain is 140 dB. The input offset voltage of this operational amplifier is 0.41 μV. Both the power supply rejection ratio and the common-mode rejection ratio have values above 140 dB, with the common-mode rejection ratio reaching as high as 165.4 dB. The transimpedance conversion circuit consists of the operational amplifier designed in this paper. The test results show that the operational amplifier has a certain application value in the transimpedance amplification circuit.

A High CMRR Differential Difference Amplifier Employing Combined Input Pairs for Neural Signal Recordings.

This article introduces a Combined .symmetrical and complementary Input Pairs (CIP) of a Differential Difference Amplifier (DDA), to boost the total Common-Mode Rejection Ratio (CMRR) for multi-channel neural signal recording. The proposed CIP-DDA employs three input pairs (transconductors). The dc-coupled input neural signal connection, via the gate terminal of the first transconductor, yields a high input impedance. The high-pass corner frequency and dc quiescent operation point are stabilized by the second transconductor. The calibration path of differential-mode gain and Common-Mode Feedback (CMFB) is provided by the proposed third transconductor. The parallel connection has no need for extra voltage headroom of input and output. The proposed CIP-DDA is targeted at integrated circuit realization and designed in a 0.18-μm CMOS technology. The proposed CIP-DDAs with system CMFB achieve an average CMRR of 103 dB, and each channel consumes circa 3.6 μW power consumption.

An 800MΩ-Input-Impedance 95.3dB-DR Δ-ΔΣ AFE for Dry-Electrode Wearable EEG Recording.

Non-invasive, closed-loop brain modulation offers an accessible and cost-effective means of evaluating and modulating one's mental and physical well-being, such as Parkinson's disease, epilepsy, and sleep disorders. However, wearable EEG systems pose significant challenges for the analog front-end (AFE) circuits in view of µV-level EEG signals of interest, multiple sources of interference, and ill-defined skin contact. This paper presents a direct-digitization AFE tailored for dry-electrode scalp EEG recording, characterized by wide input dynamic range (DR) and high input impedance. The AFE utilizes a second-order 5-bit delta-delta sigma (Δ-ΔΣ) ADC to shape DC electrode offset (DEO) and low-frequency disturbances while retaining high accuracy. A non-inverting pseudo-differential instrumentation amplifier (IA) embedded in the ADC ensures high input impedance (Zin) and common-mode rejection ratio (CMRR). Fabricated in a standard 0.18-μm CMOS process, the AFE delivers 700-mVpp input signal range, 95.3-dB DR, 87-dB SNDR, and 800-MΩ input impedance at 50 Hz while consuming 88.4µW from a 1.2 V supply. The benefits of high DR and high input impedance have been validated by dry-electrode EEG measurement.

Design of ECG circuits for wearable devices

Heart diseases have become more and more prominent in recent years. ECG signals can accurately reflect the health of hearts during the detection process. The use of wearable ECG devices requires low power consumption, a high common-mode rejection ratio, and minimal noise. Traditional research has concentrated on lowering the circuit's overall power dissipation, which typically results in less current flowing through the amplifier but higher circuit noise. Therefore, this places higher demands on the amplifier in the circuit. Electronic devices are becoming smaller due to the rapid development of semiconductor technology. Amplifiers designed for semiconductor devices can effectively solve the problems mentioned above. The circuit created in this study has a low power need, a high common-mode rejection ratio, is compact, has a high input impedance, and has a low input-referred noise level. In addition, LT-Spice software was used to design and simulate the circuit, and the results were analyzed and calculated accordingly. The circuit meets the requirements of the project design. The frequency range of the circuit is 1mHz - 227.9Hz. The differential gain of the circuit is 36.6dB. The integrated input-fred noise is 3.94uV. The total consumption of electricity is 4.67W. These data indicate that the circuit has a high gain in the frequency range of ECG signals, which can filter out other interference signals. It also solves the problems of power consumption and noise.

A low-power low-noise amplifier with high CMRR for wearable healthcare applications

Low-noise and low-power operation are important parameters of amplifier intended for wearable healthcare applications. However, along with these parameters the amplifier must be able to deliver high Common Mode Rejection Ratio (CMRR) for mitigating the effect of 50/60 Hz interference. This paper reports capacitively coupled-capacitive feedback amplifier based on Self Cascode Current Mirror-II (SCCM-II) Operational Transconductance Amplifier (OTA). The obtained results for proposed SCCM-II OTA based amplifier shows gain of 39.79 dB, input referred noise of 2.64 μVrms, bandwidth of 0.794-343.4 Hz, area consumption of 0.154 μm2, power consumption of 2.54 μW with ±0.9 V supply. The noise efficiency factor and CMRR values for proposed amplifier are 3.87 and 122.1 dB, respectively. In-depth theoretical interpretations and mathematical modeling of amplifier are validated in 0.18μm standard CMOS process using BSIM3V3 MOS device models. The Gaussian distribution plots of proposed amplifier for 200 Monte-Carlo iterations infer mean values for gain and CMRR are 39.79 dB and 112.96 dB which are very close to their nominal values. The proposed amplifier has been compared with conventional approach as well as with literature and improvement in results is observed in terms of input referred noise, power and CMMR. These advantages of the proposed amplifier make it suitable for non-invasive wearable healthcare applications.

Design of low-noise low-power ECG amplifier circuit with high integration level

Electrocardiogram (ECG) is a common tool in medicine and is an important indicator for diagnosing many diseases. Nowadays, aspects such as low noise, low power, and high integration have become important indicators for ECG circuit design. Also, due to the low amplitude of ECG signals, ECG circuits need to have high gain to ensure accurate signal detection and analysis. Second, ECG signals are usually subject to interference from other parts of the body, so a high common mode rejection ratio (CMRR) is required to suppress these interfering signals. In this paper, we propose an ECG circuit composed of an amplifier with a drive right leg circuit (DRL) using pseudo-resistors as well as capacitors to improve the common instrumentation amplifier. The simulation using industrial-grade simulation software LTspice shows that the circuit has a voltage of 1.8 V, a bandwidth of 17 mHz-1 KHz, a gain of 55 dB, and an INR of 3.4 μVrms, and because the signal amplifier part of this circuit design consists of only pseudo-pseudo-resistors, capacitors, and mos tubes. Therefore, it has a smaller size and a higher degree of integration. In addition, the circuit has less power loss for the same amplification design. Overall, this design has excellent characteristics such as low noise, low power, and small size.

A Wireless, High-Quality, Soft and Portable Wrist-Worn System for sEMG Signal Detection.

The study of wearable systems based on surface electromyography (sEMG) signals has attracted widespread attention and plays an important role in human-computer interaction, physiological state monitoring, and other fields. Traditional sEMG signal acquisition systems are primarily targeted at body parts that are not in line with daily wearing habits, such as the arms, legs, and face. In addition, some systems rely on wired connections, which impacts their flexibility and user-friendliness. This paper presents a novel wrist-worn system with four sEMG acquisition channels and a high common-mode rejection ratio (CMRR) greater than 120 dB. The circuit has an overall gain of 2492 V/V and a bandwidth of 15~500 Hz. It is fabricated using flexible circuit technologies and is encapsulated in a soft skin-friendly silicone gel. The system acquires sEMG signals at a sampling rate of over 2000 Hz with a 16-bit resolution and transmits data to a smart device via low-power Bluetooth. Muscle fatigue detection and four-class gesture recognition experiments (accuracy greater than 95%) were conducted to validate its practicality. The system has potential applications in natural and intuitive human-computer interaction and physiological state monitoring.

C-Band optical 90-degree hybrid using thin film lithium niobate.

The integrated optical 90-degree hybrid is a crucial component for coherent receivers. Here, we simulate and fabricate a 4 × 4 multimode interference coupler as a 90-degree hybrid using thin film lithium niobate (TFLN). The device features low loss (0.37 dB), high common mode rejection ratio (over 22 dB), compact footprint, and small phase error (below 2°) within the whole C-band experimentally, which is promising for integration with coherent modulators and photodetectors for TFLN-based high-bandwidth optical coherent transceivers.

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 GΩ with a chip area of 0.09 mm2.

A Measurement System with High Precision and Large Range for Structured Surface Metrology Based on Atomic Force Microscope

With the rapid and continuous development of nanomanufacturing technology, the demands for both large range and high precision metrology of structured surfaces are becoming increasingly urgent. This paper proposes a metrological measurement system based on a commercial atomic force microscope. By using the nano-positioning platform from SIOS, the measurement range of the system expands from 110 μm × 110 μm × 20 μm to 25 mm × 25 mm × 5 mm. A signal amplifier with low noise and a high common mode rejection ratio that decreases the noise level of the measurement system to 2 nm is designed. Integration of the metrological system, signal processing, and calibration of the whole system is introduced. Three experimental studies are carried out on an ultrahigh step, an atomic deposition grating, and a cutting tool. The experimental results demonstrate high measurement repeatability and reproducibility in both vertical and lateral directions. By repeating 10 times of measurement, the expended uncertainties of the step and the grating measurement are 36.24 nm and 0.60 nm, respectively. Additionally, measurement of a cutting tool tip is conducted to illustrate the performance of the system. The Ra and Rz values of the tool tip arc ripple are 29.8 nm and 189 nm, respectively.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

Design of ECG Signals Filter Circuit Based on OTA Filtering

The ECG signal reflects the physiological characteristics of the heart to a certain extent and is an extremely important clinical reference for the diagnosis, treatment, and prevention of cardiovascular diseases. However, the ECG signal is affected by various noises during the acquisition process, especially the 50Hz noise from power lines which makes the diagnosis and analysis of ECG difficult. In this paper, a transconductance amplifier with strong practical applications is proposed and designed to filter out interference from ECG signals in power lines, based on the characteristics of ECG signals and the ability of differential signals to effectively resist external common-mode noise. This amplifier is able to effectively filter out 50Hz interference from power lines and features a high common-mode rejection ratio and low power consumption, in addition to using relatively few components and low production costs.

Design of current controlled instrumental amplifier by using complementary metallic oxide semiconductor technology

<p>In this paper, a complementary metal oxide semiconductor (CMOS) instrumental amplifier was designed and implemented in order to provide the possibility of controlling the current and voltage gain. The proposed instrumentation amplifier consists of three conveyors with active resistor. The parasitic resistance value (Rx) was reduced with a large bandwidth level in addition to achieving a high common mode rejection ratio (CMRR). Simulation was performed by using 0.35μm CMOS technology by using the advanced design system (ADS) software. The results obtained prove that the proposed circuit has a good efficiency with higher degree of CMRR in comparison with other amplifiers designed and implemented in other similar works.</p>

Analysis and Measurements of an Urea Biosensor Based on Instrumentation Amplifier Chip With Cross-Coupled Technique

In this work, we design a high common-mode rejection ratio (CMRR) and low unity gain frequency (UGF) cross-coupled instrumentation amplifier (CCIA). This design was implemented by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process technology. By using the three proposed cross-coupled operational amplifier, the CCIAs was designed with the power supply of +1.8 and −1.8 V. The instrumentation amplifier (IA) achieved a voltage gain of 56.92 dB with a CMRR of 126.08 dB. This IA was applied on an arrayed RuO2 urea biosensor as a readout circuit. Moreover, the sensing characteristics of the urea biosensor were analyzed. The experimental results show that our arrayed RuO2 urea biosensor combined with CCIA has a good average sensitivity of 2.933 mV/(mg/dL) and a linearity of 0.998. With the proposed IA, an effective measurement system can be achieved due to simplicity, convenience, and low cost.

A current mode instrumentation amplifier with high common-mode rejection ratio designed using a novel fully differential second-generation current conveyor

This study presents a high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR. The design is based on a fully differential second-generation current conveyor block with a novel circuit design following by a current subtracting stage. The CMIA is designed and laid out in 130 nm CMOS technology operating under ± 1.2 V supply voltage in Cadence software. The post-layout simulation results show that the CMIA achieves low-frequency voltage and current CMRR- BW of 228.8 dB–10 kHz and 246 dB–10.6 kHz, respectively, with PSRR + /PSRR- of 108.2 dB/99.7 dB, power consumption of 507 µW, and a core area of 0.0015 mm2. The unique quality of the circuit is that, it does not need well-matched active blocks, but inherently improves CMRR, bandwidth, and PSRR; hence it gains an excellent choice for integration.

Differential Input First-Order Universal Filter with Two DVCC+s

In this paper, a differential-input plus-type differential voltage current conveyor-based first-order universal filter is designed. This voltage-mode filter uses a grounded capacitor. In addition, it can provide all the noninverting and inverting first-order universal filter responses. The circuit provides high common-mode rejection ratio of about 76.5 dB. Nevertheless, it needs a single matching problem and comprises two floating resistors. Quadrature oscillator (QO) design is obtained using this filter as an application example. The designed filter and QO circuits are simulated through the SPICE program, and some experimental studies are carried out using AD844 ICs to verify the theory.

Common-Mode Driven Synchronous Filtering of the Powerline Interference in ECG

Powerline interference (PLI) is a major disturbing factor in ground-free biopotential acquisition systems. PLI produces both common-mode and differential input voltages. The first is suppressed by a high common-mode rejection ratio of bioamplifiers. However, the differential PLI component evoked by the imbalance of electrode impedances is amplified together with the diagnostic differential biosignal. Therefore, PLI filtering is always demanded and commonly managed by analog or digital band-rejection filters. In electrocardiography (ECG), PLI filters are not ideal, inducing QRS and ST distortions as a transient reaction to steep slopes, or PLI remains when its amplitude varies and PLI frequency deviates from the notch. This study aims to minimize the filter errors in wide deviation ranges of PLI amplitudes and frequencies, introducing a novel biopotential readout circuit with a software PLI demodulator–remodulator concept for synchronous processing of both differential-mode and common-mode signals. A closed-loop digital synchronous filtering (SF) algorithm is designed to subtract a PLI estimation from the differential-mode input in real time. The PLI estimation branch connected to the SF output includes four stages: (i) prefilter and QRS limiter; (ii) quadrature demodulator of the output PLI using a common-mode driven reference; (iii) two servo loops for low-pass filtering and the integration of in-phase and quadrature errors; (iv) quadrature remodulator for synthesis of the estimated PLI using the common-mode signal as a carrier frequency. A simulation study of artificially generated PLI sinusoids with frequency deviations (48–52 Hz, slew rate 0.01–0.1 Hz/s) and amplitude deviations (root mean square (r.m.s.) 50–1000 μV, slew rate 10–200 μV/s) is conducted for the optimization of SF servo loop settings with artificial signals from the CTS-ECG calibration database (10 s, 1 lead) as well as for the SF algorithm test with 40 low-noise recordings from the Physionet PTB Diagnostic ECG database (10 s, 12 leads) and CTS-ECG analytical database (10 s, 8 leads). The statistical study for the PLI frequencies (48–52 Hz, slew rate ≤ 0.1 Hz/s) and amplitudes (≤1000 μV r.m.s., slew rate ≤ 40 μV/s) show that maximal SF errors do not exceed 15 μV for any record and any lead, which satisfies the standard requirements for a peak ringing noise of &lt; 25 μV. The signal-to-noise ratio improvement reaches 57–60 dB. SF is shown to be robust against phase shifts between differential- and common-mode PLI. Although validated for ECG signals, the presented SF algorithm is generalizable to different biopotential acquisition settings via surface electrodes (electroencephalogram, electromyogram, electrooculogram, etc.) and can benefit many diagnostic and therapeutic medical devices.