High Aspect Ratio Through-silicon Research Articles

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD.

In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V3D3)) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V3D3) was integrated in high aspect ratio TSV (10 × 100 μm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.

Autocatalytic Deposition of Nickel–Boron Diffusion Barrier onto Diazonium-Treated SiO2 for High Aspect Ratio Through-Silicon Via Technology in 3D Integration

Autocatalytic Deposition of Nickel–Boron Diffusion Barrier onto Diazonium-Treated SiO₂ for High Aspect Ratio Through-Silicon Via Technology in 3D Integration

Superconformal Film Growth: From Smoothing Surfaces to Interconnect Technology.

ConspectusElectronics manufacturing involves Cu electrodeposition to form 3D circuitry of arbitrary complexity. This ranges from nanometer-wide interconnects between individual transistors to increasingly large multilevel intermediate and global scale on-chip wiring. At larger scale, similar technology is used to form micrometer-sized high aspect ratio through-silicon vias (TSV) that facilitate chip stacking and multilevel printed circuit board (PCB) metallization. Common to all of these applications is void-free Cu filling of lithographically defined trenches and vias. While line-of-sight physical vapor deposition processes cannot accomplish this feat, the combination of surfactants and electrochemical or chemical vapor deposition enables preferential metal deposition within recessed surface features known as superfilling. The same superconformal film growth processes account for the long-reported but poorly understood smoothing and brightening action provided by certain electroplating additives. Prototypical surfactant additives for superconformal Cu deposition from acid-based CuSO4 electrolytes include a combination of halide, polyether suppressor, sulfonate-terminated disulfide, and/or thiol accelerator and possibly a N-bearing cationic leveler. Many competitive and coadsorption dynamics underlie functional operation of the additives. Upon immersion, Cu surfaces are rapidly covered by a saturated halide layer that makes the interface more hydrophobic, thereby supporting the formation of a polyether suppressor layer. Also, halide serves as a cosurfactant supporting the adsorption of amphiphilic molecular disulfide species on the surface while inhibiting copper sulfide formation and incorporation into the growing deposit. Furthermore, the dangling hydrophilic sulfonate end group of the accelerator enables activated metal deposition by hindering polyether suppressor assembly. A common thread in superconformal feature filling is additive-derived positive feedback of the metal deposition reaction within recessed or re-entrant regions. For submicrometer features or optically rough surfaces, area reduction that accompanies the motion of concave surface segments results in the most strongly bound adsorbates' enrichment, which for the suppressor-accelerator systems is the sulfonate-terminated disulfide accelerator species. The superfilling and smoothing process is quantitatively captured by the curvature-enhanced adsorbate coverage mechanism. For larger features, such as TSV, whose depths approach the thickness of the hydrodynamic boundary layer, significant compositional and electrical gradients couple with the metal deposition process to give a negative differential resistance and related nonlinear effects on morphological evolution. For certain suppressor-only electrolytes, remarkable bottom-up feature filling occurs where metal deposition disrupts inhibiting adsorbates at the bottom of the TSV or overruns the ability of the suppressor to form due to kinetic or transport limitations. Because the electrical response to changes in interface chemistry is more rapid than mass transport processes, deposition on planar substrates proceeds by bifurcation into passive and active zones, generating Turing patterns. On patterned substrates, active zone development is biased toward the most recessed regions. The distinction between packaging and on-chip metallization will be blurred as the dimensions of the former merge with those of early day on-chip 3D metallization.

Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration.

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.

Superconducting High-Aspect Ratio Through-Silicon Vias with DC-Sputtered Al for Quantum 3D integration

This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of $300~\mu \text{m}$ -deep and $50~\mu \text{m}$ -wide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 $\text{m}\Omega $ at room temperature and superconductivity below 1.28 K were measured by a cross-bridge Kelvin resistor structure. This work thus demonstrates the fabrication of functional superconducting interposer layers, suitable for high-density 3D integration of silicon-based quantum computing architectures.

Effect of Ultrasound on Copper Filling of High Aspect Ratio Through-Silicon Via (TSV)

Since voids and seams are usually formed during the process of filling TSVs with high aspect ratio, good methods that can achieve the superfilling of TSVs are eagerly needed. This paper presents a new copper electroplating method with the assistance of ultrasound. Result shows that ultrasound cannot only improve the TSV filling quality but also can quicken the filling rate. Ultrasounds with different powers are applied to explore the most optimized condition for TSV filling. When ultrasonic power is set as 105 W, TSVs with the diameters of 20 μm and depths of 200 μm are all fully filled in 5 hours. Additionally, acoustic streaming and cavitation effect conducted by ultrasound during the TSV filling process are also analyzed, which contributes to increasing the mass transport process and reducing the concentration polarization of electrodes.

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

Microfluidic cooling technology is a promising thermal solution for high-performance three-dimensional integrated circuits (3D ICs). However, the integration of microfluidic cooling into 3D ICs inevitably impacts tier-to-tier through-silicon vias (TSVs) by increasing their length and diameter (for a fixed aspect ratio). To address this challenge, this paper presents the fabrication of very high-aspect ratio (23:1) TSVs within a microfluidic pin-fin heat sink using two types of silicon etch masks. Void-free TSVs are electrically characterized using X-ray inspection and four-point resistance measurements.

The Limitation and Optimization of Bottom-Up Growth Mode in Through Silicon Via Electroplating

An analytical model is developed for the bottom-up growth mode observed in the electroplating of high aspect ratio through-silicon vias (TSVs). The effects of various factors, including the feature geometry, the suppression effect of the suppressive additives and the applied electric current, on the filling process are discussed. The process window for void-free filling and its narrowing down with the reduction of TSV footprint are demonstrated in simulation. The motivation to introduce ramping current in the electroplating of high aspect ratio TSVs is analyzed. Reduced plating time is demonstrated for stepwise ramping of the input current. Using the proposed analytical model, a simulation methodology for fast searching of the optimal plating conditions in multiple-step plating schemes is introduced.

(Invited) Metrology for 3D Integration

Three-dimensional stacked integrated circuits (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through-silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. The implementation 3DS-IC also presents significant metrology challenges. This talk will give an overview of the metrology needs for 3DS-IC, identify solutions, and describe work towards the development of standards to support the 3D ecosystem. One of these standards under development is investigating methods for identifying and characterizing voids between bonded wafers. Wafer bonding in a 3DS-IC process is typically an intermediate step. After bonding, one or both of the wafers will undergo processes such as thinning, thin film deposition, lithography, and patterning. The presence of voids between the wafers will cause significant stack thickness variation, which can lead to failure at one or more of these steps. A number of tools can be used to identify and/or characterize voids; this standard will provide members of the 3DS-IC community with guidance for choosing the tool or tools that will best address the specific need. Preliminary results from a round robin experiment, involving approximately 20 laboratories, will be shown. This experiment uses as a test structure a bonded wafer pair with a number of voids patterned into one of the wafers before bonding. The sizes of the programmed voids range from 0.5 μm to 300 μm with depths of 15 nm to 1200 nm and are placed in isolated, semi-dense, and dense patterns. A scanning acoustic microscope image of one instance of the test chip with patterned voids is shown in the figure.

(Invited) Metrology for 3D Integration

Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through-silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. Each of these new fabrication steps is associated with metrology challenges. The SEMI 3DS-IC Committee is developing a set of guides to assist the 3DS-IC community in addressing these challenges by identifying metrology solutions. In this paper we provide an overview of the metrology needs for 3DS-IC, identify metrology solutions, and provide examples from SEMI standards describing methods for characterizing the quality and strength of bonds between wafers.

Fully back-end TSV process by Cu electro-less plating for 3D smart sensor systems

A fully back-end process for high-aspect ratio through-silicon vias (TSVs) for 3D smart sensor systems is developed. Atomic layer deposition of TiN provides a highly conformal barrier as well as a seed layer for metal plating. Cu electro-less plating on the chemically activated TiN surfaces is applied to uniformly fill the TSVs in a significantly shorter time (2 h for 300 μm deep and 20 μm wide TSVs) than with Cu bottom-up electroplating (>20 h). The process is CMOS compatible and can be performed after the last metalization step, making it a fully back-end process (VIA-last approach). Wafers containing metal interconnections on both sides are in fact used as demonstrator. Four-terminal 3D Kelvin structures are fabricated and characterized. An average resistance value of 650 mΩ is measured for 300 μm deep TSVs with an aspect ratio of 15. The crosstalk between adjacent TSVs is also measured by means of S-parameters characterization on dedicated RF test structures. The closest TSVs (75 μm) show a reciprocal crosstalk of less than −20 dB at 30 GHz.

Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias

A conformal diffusion barrier was formed in a high aspect ratio through-silicon via using electroless plating. Dense adsorption of Pd nanoparticle catalyst on SiO2 assisted the formation of a thin electroless Co-W-B layer, upon which an electroless Cu seed layer could be deposited. The adhesion strength of the Co-W-B film was enhanced by reducing the film thickness, and the maximum strength was obtained at a thickness of 20nm. The Co-W-B layer exhibited good barrier properties against Cu diffusion to SiO2 after annealing at 300^oC, although slight diffusion of the Pd atoms in Cu was observed.

Characterizing Transport Limitations during Copper Electrodeposition of High Aspect Ratio Through-Silicon Vias

Characterizing Transport Limitations during Copper Electrodeposition of High Aspect Ratio Through-Silicon Vias

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

High Density Copper Nucleation on Ruthenium Using Commercial Plating Chemistry and Its Application to Metallization of High Aspect Ratio Through-Silicon Vias

not Available.

Advances in Wafer Level Processing and Integration for CIS Module Manufacturing

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.