High Aspect Ratio Silicon Etching Research Articles

Modeling and characterization of deeply etched multilayer resonators under partial coherent excitation via multimode optical fibers

Recently, there has been a resurgence of interest in multimode optical fibers illuminated by a white light source. Largely, in anticipation of many integrated applications in the biomedical domain and spectral sensing benefiting from the broad spectral range and high numerical aperture (NA). Along these lines, the output light from these fibers can be captured by the physics of partially coherent sources. While the Gaussian Schell model has provided a framework for studying partial coherence, to our knowledge, its impact on microstructures remains unexplored. As the sheer complexity arising from the interplay between partial coherence and microstructures transfer function has posed fundamental challenges in deciphering their response. In this work, we introduce a comprehensive numerical model paired with experimental validation to assess the performance of multilayer optical resonators, which are meticulously crafted through high aspect ratio silicon etching under the influence of a partially coherent optical source. The model studies the effects of optical fiber NA, Bragg mirror order, cavity length, and surface roughness of the microstructures on the output of the resonator. The results show that the response under standard multimode fiber (MMF, partial coherent source) has lower insertion loss, more asymmetry versus wavelength, and larger full width at half maximum than the standard single mode fiber (full coherent source). A silicon-on-insulator chip is fabricated using 130 µm deep etching of silicon for Bragg mirrors with 2.25, 3, and 3.25 µm silicon layer widths and a different number of layers. The structures are characterized using a MMF of 62.5 µm core diameter illuminated by an infrared white light source. The theoretical results have been compared with the experimental results and a good agreement has been obtained.

Deep reactive ion etching of silicon using non-ICP-based equipment

Deep reactive ion etching (DRIE) technology is one of the most important technologies in the processing of microelectronic devices and microelectromechanical system. As a necessary process in semiconductor integration, it has been widely studied in the past decades. It is known that the traditional DRIE process typically uses a plasma etching reactor equipped with inductively coupled plasma (ICP) sources to generate a high-density plasma so as to achieve high aspect ratio trenches with relatively small roughness. A cryogenic temperature control unit is typically employed as well. Here, however, we use a parallel plate RIE with rather simple structure, which is not usually used for DRIE, to obtain high aspect ratio silicon etching. With no ICP sources and no sophisticated temperature control unit, the system and experiment are now much more cost effective. Through the optimization of the processing, the etching rate of silicon can reach 440 nm/min. Finally, a 45 μm deep trench is etched in silicon with good perpendicularity. This method will greatly reduce the equipment related cost, especially for those applications that do not have extremely stringent requirement on the final etching accuracy.

Use of Hard Mask for Finer (<10 μm) Through Silicon Vias (TSVs) Etching

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

Plasma chemical etching of high-aspect-ratio silicon micro- and nanostructures

High-aspect-ratio (HAR) silicon etching of micro-and nanostructures in a time-multiplexed deep etching process (Bosch process) is reviewed, including applications, different technological methods, critical challenges, and main principles of the technologies. HAR silicon etching is an application associated primarily with micro- and nanostructures. This potentially large-scale application requires HAR etching with a high throughput and controllable profile and surface properties. The most significant effects like RIE lag, bowing, stop effect, and profile shape dependence are discussed.

Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping

AbstractBulk micromachining technology can be used to produce conducting through-wafer polysilicon interconnects, i.e., polysilicon via plugs. This paper presents the process fabrication steps of polysilicon via plugs with in-situ boron doped polysilicon material in order to develop fast one-step doping process, without additional diffusion. The via holes can be processed by high-aspect ratio silicon etching with inductively coupled plasma (ICP). Only one deep ICP etching is required if the wafer is mechanically ground (from the backside) to reduce the wafer thickness of 500 microns to a typical of 400, in order to overcome deep etching sidewall profile problems. After hole formation with ICP the via plug fabrication process continues by growing an insulating thermal oxide layer with a thickness of the order of a micron, followed by an in-situ boron doped LPCVD polysilicon growth to fill the holes with sufficient step coverage. The polysilicon growth temperature at 680°C ensures sufficient step coverage, reasonable furnace process time and enables planarization processing, such as grinding and chemical-mechanical polishing (CMP). The subsequent planar processing typically requires planarization of the polysilicon layer down to the original silicon (or oxide) surface with CMP, and some doping activation step, which usually can be performed together with some additional oxidation step. Applications of the via plugs in the field of silicon-based sensors or actuators enable significant reduction of the front surface wiring density, which opens additional space for denser packing or other desired components.

Fabrication and Characterization of Pzt Thin-Film on Bulk Micromachined Si Motion Detectors

AbstractMotion detectors consisting of Pb(ZrxTi(1−x))O3 (PZT) thin films, between platinum electrodes, on micromachined silicon compound clamped-clamped or cantilever beam structures were fabricated using either hot KOH or High Aspect Ratio Silicon Etching (HARSE) to micromnachine the silicon. The beams were designed such that a thicker region served as a test mass that produced stress at the top of the membrane springs that supported it when the object to which the detector was mounted moved. The PZT film devices were placed on these membranes to generate a charge, or a voltage, in response to the stress through the piezoelectric effect. Issues of integration of the PZT device fabrication process with the two etching processes are discussed. The effects of PZT composition and device geometry on the response of the detectors to motion is reported and discussed.