Hierarchical Search Block-matching Algorithm Research Articles

Hierarchical stochastic fast search motion estimation algorithm

Many fast search motion estimation algorithms have been developed to reduce the computational cost required by full-search algorithms. Fast search motion estimation techniques often converge to a local minimum, providing a significant reduction in computational cost. The motion vector measurement process in fast search algorithms is subject to noise and matching errors. Therefore researchers have investigated the use of Kalman filtering in order to seek optimal estimates. In this work, the authors propose a new fast stochastic motion estimation technique that requires 5% of the total computations required by the full-search algorithm, and results in a quality that outperforms most of the well-known fast searching algorithms. The measured motion vectors are obtained using a simplified hierarchical search block-matching algorithm, and are used as the measurement part of the Kalman filter. As for the prediction part of the filter, it is assumed that the motion vector of a current block can be predicted from its four neighbouring blocks. Using the predicted and measured motion vectors, the best estimates for motion vectors are obtained. Using standard methods of accuracy measurements, results show that the performance of the proposed technique approaches that of the full-search algorithm.

Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems

3-D video will be the most prominent video technology in the next generation. Among the 3-D video technologies, stereo video systems are considered to be realized first in the near future. Stereo video systems require double bandwidth and more than twice the computational complexity relative to mono-video systems. Thus, an efficient coding scheme is necessary for transmitting stereo video. In this paper, a new structure of prediction core in stereo video coding systems is proposed from the algorithm level to the hardware architecture level. The joint prediction algorithm (JPA), which combines three prediction schemes, is proposed for high coding efficiency and low computational complexity. It makes the system outperform MPEG-4 temporal scalability and simple profile by 2-3 dB in rate-distortion performance. Besides, JPA also utilizes the characteristics of stereo video and successfully reduces about 80% computational complexity. Then, a new hardware architecture of the prediction core based on JPA and a modified hierarchical search block-matching algorithm is proposed. With a special data flow, no bubble cycles exist during the block-matching process. The proposed architecture also adopts the near-overlapped candidates reuse scheme to save the heavy burden of data access. Besides, both on-chip memory requirement and off-chip memory bandwidth can be reduced by the proposed new scheduling. Compared with the hardware requirement for the implementation of full search block-matching algorithm, only 11.5% on-chip SRAM and 3.3% processing elements are needed with a tiny PSNR drop, making it area-efficient while maintaining high stereo video quality and processing capability

A memory efficient motion estimator for three step search block-matching algorithm

This paper describes a memory efficient array architecture with data-rings for the 3-step hierarchical search block-matching algorithm (3SHS). With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control scheme and reduce latency, respectively. In addition, we utilize the three-half-search-area scheme and circular addressing method to reduce external memory access and memory size, respectively. The results demonstrate that the array architecture with a memory efficient scheme requires a smaller memory size and low I/O bandwidth. It also provides a high normalized throughput solution for the 3SHS.

A novel hierarchical-search block matching algorithm and VLSI architecture considering the spatial complexity of the macroblock

We propose a novel hierarchical-search block matching algorithm for motion estimation, which adaptively selects an initial search level based on the spatial complexity of a matching block. It relies on a simple computation of the pixel intensity variation in the current macroblock. We demonstrate its effectiveness in two aspects: the performance and the computational cost. A hardware architecture and a VLSI realization of this algorithm with half-pel motion estimation and motion compensation are also presented. The proposed algorithm greatly reduces the computations required in the existing hierarchical-search block matching algorithms while achieves virtually identical performance to them.

Improved hierarchical search block matching algorithmby using multiple motion vector candidates

The authors describe a hierarchical search block matching algorithm capable of handling large motion in real time motion estimation for existing video compression standards. The algorithm uses multiple motion vector candidates based on an interframe difference measure and a spatial motion-field correlation, respectively. In MPEG-2 application, the encoder adopting the proposed algorithm provides nearly the same performance as the conventional encoder adopting the full search block matching algorithm, with only 0.9% computational complexity for motion estimation.

Parallel architectures for 3-step hierarchical search block-matching algorithm

The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems. >

A motion estimator for low bit-rate video codec

A novel component performing motion estimation is presented. This chip is designed based on the three-step hierarchical search block-matching algorithm and can be applied to image communication on ISDN (integrated services digital network) (H.261 standard), MPEG, TV transmission, HDTV (high-definition television), etc. The practical architectural design techniques and the chip features are discussed. This component has the following features: unified execution steps, low latency delay, low I/O bandwidth, regular hardware structure, and single-chip or cascaded configurations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>