Hierarchical Multiprocessor System Research Articles

Three Round Adaptive Diagnosis in Hierarchical Multiprocessor Systems

System level diagnosis is an important technique for fault detection and location in multiprocessor computing systems. Adaptive diagnosis, proposed by Nakajima, is a practical system level diagnostic scheme; the main design objective of an adaptive diagnostic scheme is to reduce the number of test rounds, as well as the total number of tests. The hierarchical crossed cube draws upon constructions used within both the hypercube and the crossed cube, giving it many desirable features such as symmetry and logarithmic diameter, making it suitable for massively parallel systems with thousands of processors. In this paper, we first show that the diagnosability of a hierarchical crossed cube, HCCk,n, is k+n, and then propose a scheme that completely diagnoses a HCCk,n within three test rounds, and at most N+⌈(k+n+2)/2⌉ × ⌊(k+n+2)/2⌋ tests, where N=2k+2n is the number of vertices of HCCk,n. Our diagnostic scheme has the optimal number of test rounds. Moreover, most of our proofs are applicable not just to hierarchical crossed cubes but also to hierarchical interconnection networks formed by replacing crossed cubes with other appropriate interconnection networks.

Simulation of hierarchical multiprocessor database systems

The paper is dedicated to issues concerning simulation and analysis of hierarchical multiprocessor systems oriented to database applications. Requirements for a parallel database system model are given. A survey and comparative analysis of known parallel database system models are presented. A new multiprocessor database system model is introduced. This model allows us to simulate and evaluate arbitrary hierarchical multiprocessor configurations in the context of the OLTP class database applications. Examples of using the database multiprocessor model for simulation study of multiprocessor database systems are presented.

Grasp: Visualizing the behavior of hierarchical multiprocessor real-time systems

Trace visualization is a viable approach for gaining insight into the behavior of complex distributed real-time systems. Grasp is a versatile trace visualization toolset. This paper presents its unique visualization capabilities for hierarchical multipro- cessor systems, including partitioned and global multiprocessor scheduling with migrating tasks and jobs, communication between jobs via shared memory and message passing, and hierarchical scheduling in combination with multiprocessor scheduling. Its flexible plugin infrastructure allows for easy extension with custom visualization and analysis techniques for automatic trace verification. Grasp is freely available on the web 1 . Modern real-time systems are becoming increasingly more complex, with many tasks executing concurrently on many processors, making it difficult to understand the system be- havior. A popular trend in coping with the vast number of tasks and the resulting interferences between them is to hide tasks inside components and to integrate the system from those components. This approach requires hierarchical scheduling, which has been covered extensively in the literature for unipro- cessor systems. Recently, the real-time literature has been in- vestigating applying hierarchical scheduling to multiprocessor platforms. In this paper we address the problem of how to provide insight into complex interaction patterns between jobs executing in a hierarchical multiprocessor system. Several approaches are available for tackling the complexity of modern software systems. Ideally, every system would be meticulously documented, providing a formal yet concise description of the emergent system behavior. However, this is a long and costly process without immediate effects (such as additional functionality) and is therefore not common in prac- tice. Examples of poorly documented code and system designs are abundant. The description of the dynamic system behavior therefore needs to be extracted from existing systems. There are modeling and verification tools available, which rely on the developers analyzing the implementation and constructing its model. These tools then employ formal methods to verify the behavior of the extracted model against an abstract model. The state of the art modeling and verification techniques, however, are not scalable and therefore can be applied to verify only a small portion of the entire system. 1The work presented in this paper was supported in part by the European ITEA2-CANTATA project. The Grasp toolset together with example traces is available for Linux, Mac and Windows at http://www.win.tue.nl/ mholende/grasp.

Modeling distributed real-time applications with specification PEARL

The methodology of hardware/software co-design of embedded control systems with Specification PEARL is presented. Hardware and software are modeled with the language Specification~PEARL, which has its origins in standard Multiprocessor~PEARL. Its usefulness is enhanced for modeling hierarchical and asymmetrical multiprocessor systems, and by additional parameters for schedulability analysis. Graphical symbols are introduced for its constructs to enable graphical modeling while maintaining the semantical background. It is meant to be a superlayer for programs, based on the PEARL programming model. To model program tasks, Timed State Transition Diagrams have been defined. The model of a co-designed system is verified for feasibility with co-simulation. The resulting information should be used when considering changes in a current design with the goal of producing a temporally feasible model. To support dynamic re-configurations, configuration management is introduced into the models. Since UML is becoming a de facto standard also for designing embedded control systems, and since Timed State Transition Diagrams and State Chart Diagrams share great similarity, an interface of the methodology to UML 2 is defined, using UML's extension mechanisms.

Dependability evaluation of interconnection networks

A novel method aiming at evaluating dependability of multiprocessor systems is presented. The systems under evaluation can incorporate various interconnection systems namely crossbar, multiple-bus, single and multiple path multistage. The analysis can also be employed in the case of hierarchical multiprocessor systems.

Clarifications and corrections to 'performance analysis of a generalized class of m-level hierarchical multiprocessor systems' (Mar 1992 129-138)

Several items in the above-titled work (ibid., vol.3, no.2, pp.129-138, Mar. 1992) are clarified and corrected.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Bandwidth availability of m-level hierarchical multiprocessor systems

In previous work, we proposed an m-level hierarchical multiprocessor system. The proposed system reduces the network complexity by employing m levels of hierarchy. The system performance was analyzed, and the results showed that, for a higher rate of local requests, the system performed close to the crossbar system, and better than a typical multiple-bus system (with the number of buses equal to half the number of processors). In this paper, we study the effect of failures on the performance of the m-level hierarchical multiprocessor systems. We develop analytical modeling techniques to compute the reliability and the bandwidth availability of the m-levelsystem, for hierarchically nonuniform reference (HNR) and uniform reference (UR) models. The results obtained for the m-level system are compared with those of the crossbar and multiple-bus systems.

Performance analysis of a generalized class of m-level hierarchical multiprocessor systems

The performance of the m-level hierarchical multiprocessor system is analyzed in terms of the system bandwidth for both hierarchically nonuniform reference and uniform reference models. The results show that for a higher rate of local requests (requests to memory modules within the same cluster) the m-level system performs fairly close to the crossbar system and outperforms a typical multiple-bus system (with the number of buses equal to half the number of processors). The bandwidth of the m-level system is evaluated for different numbers of levels, and the results are compared with those of a crossbar system (m=1).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Approximate performance/cost analysis of m-level hierarchical multiprocessor systems

In previous work, we introduced and analyzed a generalized class of m -level hierarchical multiprocessor systems [1]. The m levels of hierarchy employed by these systems allowed the use of relatively smaller crossbar switches to support processor-memory communication at the local, nonlocal, and global levels. The analysis showed that, for high rate of local requests the m -level system offers a BandWidth (BW) close to that of a crossbar system and better than that of a typical multiple-bus system (with the number of buses equal to half the number of processors). In this paper, the cost effectiveness of the m -level hierarchical multiprocessor system is evaluated in terms of a cost-related performance measure (BW/Cost). Based on an approximate cost analysis, the bandwidth-to-cost ratio of both the m -level and the crossbar multiprocessor systems has been determined, for hierarchically nonuniform reference model. It has been observed that the m -level system is more effective than the crossbar system for medium and large scale multiprocessor systems.

Load balancing strategies for a parallel ray-tracing system based on constant subdivision

Static and dynamic load balancing strategies for a multiprocessor system for a ray tracing algorithm based on constant subdivision are presented. An object space is divided into regular cubes (subspaces), whose boundary planes are perpendicular to the coordinate axes, and these are allocated to the processors in the system. Here, load balancing among the processors is the most important problem. Firstly, in a category of static load balancing, strategies for mapping the subspaces into the processors are evaluated by simulation. Moreover, we propose a hierarchical multiprocessor system in order to realize dynamic load balancing with the static one. Its architecture can overcome the limitation of the static load balancing in a large scale multiprocessor system.

A parallel processor system for three-dimensional color graphics

This paper describes the hardware architecture and the employed algorithm of a parallel processor system for three-dimensional color graphics. The design goal of the system is to generate realistic images of three-dimensional environments on a raster-scan video display in real-time. In order to achieve this goal, the system is constructed as a two-level hierarchical multi-processor system which is particularly suited to incorporate scan-line algorithm for hidden surface elimination. The system consists of several Scan-Line Processors (SLPs), each of which controls several slave PiXel Processors (PXPs). The SLP prepares the specific data structure relevant to each scan line, while the PXP manipulates every pixel data in its own territory. Internal hardware structures of the SLP and the PXP are quite different, being designed for their dedicated tasks. This system architecture can easily execute scan-line algorithm in parallel by partitioning the entire image space and allotting one processor element to each partition. The specific partition scheme and some new data structures are introduced to exploit as much parallelism as possible. In addition, the scan-line algorithm is extended to include smooth-shading and anti-aliasing with the aim of rendering more realistic images. These two operations are performed on a per-scan-line basis so as to preserve scan-line and span coherence. Performance estimation of the system shows that a typical system consisting of 8 SLPs and 8×8 PXPs can generate, in every 1/15th of a second, the shadowed image of a three-dimensional scene containing about 200 polygons.