Hierarchical Memory Machine Research Articles

An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU

An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU

Adapting to Hostile Architectural Environments

Adapting to Hostile Architectural Environments

Renumbering unstructured grids to improve the performance of codes on hierarchical memory machines

The performance of unstructured grid codes on workstations and distributed memory parallel computers is substantially affected by the efficiency of the memory hierarchy. This efficiency essentially depends on the order of computation and numbering of the grid. Most grid generators do not take into account the effect of the memory hierarchy when producing grids so application programmers must renumber grids to improve the performance of their codes. To design a good renumbering scheme a detailed runtime analysis of the data movement in an application code is needed. Thus, a memory hierarchy simulator has been developed to analyse the effect of existing renumbering schemes such as bandwidth reduction, the Greedy method, colouring, random numbering and the original numbering produced by the grid generator. The renumbering is applied to either vertices, edges, faces or cells and two algorithms are proposed to consistently renumber the other entities used in the solver. The simulated and actual timings show that bandwidth reduction and Greedy methods give the best performance on IBM RS/6000, SGI Indy, SGI Indigo and SGI Power Challenge machines for three-dimensional Poissons's, Maxwell's and the Euler equations solvers. The improvement in performance is over a factor of two for applications with large grids and a high ratio of memory-accesses to computation. This factor is even higher for memory hierarchies with small caches.

Interprocedural Array Region Analyses

Many program optimizations require exact knowledge of the sets of array elements that are referenced in or that flow between statements or procedures. Some examples are array privatization, generation of communications in distributed memory machines, or compile-time optimization of cache behavior in hierarchical memory machines. Exact array region analysis is introduced in this article. These regions exactly represent the effects of statements and procedures upon array variables. To represent the flow of these data, we also introduce two new types of array region analyses: in and out regions. The intraprocedural propagation is presented, as well as a general linear framework for interprocedural analyses, which handles array reshapes. The intra- and inter-procedural propagation of array regions is implemented in pips, the interprocedural parallelizer of fortran programs developed at Ecole des mines de Paris.

Tuning LAPACK codes on hierarchical memory machines

As important as the advance of computer technology is the development of suitable software for the exploitation of computer capacity. In this sense LAPACK (Andersen et al., LAPACK User's Guide, release 1.0, SIAM, Philadelphia, 1992) appears as the most efficient library in the dense linear algebra field, obtaining good results on vector and parallel computers, and in general, on hierarchical memory machines. However, some deficiencies in the general matrix LU decomposition were detected in DGETRF subroutine. On hierarchical memory machines not only the cache and TLB faults have to be minimized, but also the page faults, which cause excessive I/O operations. The blocking strategy used by DGETRF (and LAPACK in general) makes good use of the cache memory, but does not seem to be enough to avoid unnecessary I/O operations. Therefore, DGETRF does not provide satisfactory run times for large dimension matrices. In this paper a new code using a double blocking strategy will be described, which attains better run times than DGETRF.

AN EVALUATION OF LEFT-LOOKING, RIGHT-LOOKING AND MULTIFRONTAL APPROACHES TO SPARSE CHOLESKY FACTORIZATION ON HIERARCHICAL-MEMORY MACHINES

In this paper we present a comprehensive analysis of the performance of a variety of sparse Cholesky factorization methods on hierarchical-memory machines. We investigate methods that vary along two different axes. Along the first axis, we consider three different high-level approaches to sparse factorization: left-looking, right-looking and multifrontal. Along the second axis, we consider the implementation of each of these high-level approaches using different sets of primitives. The primitives vary based on the structures they manipulate. One important structure in sparse Cholesky factorization is a single column of the matrix. We first consider primitives that manipulate single columns. These are the most commonly used primitives for expressing the sparse Cholesky computation. Another important structure is the supernode, a set of columns with identical non-zero structures. We consider sets of primitives that exploit the supernodal structure of the matrix to varying degrees. We find that primitives that manipulate larger structures greatly increase the amount of exploitable data reuse, thus leading to dramatically higher performance on hierarchical-memory machines. We observe performance increases of two to three times when comparing methods based on primitives that make extensive use of the supernodal structure to methods based on primitives that manipulate columns. We also find that the overall approach (left-looking, right-looking, or multifrontal) is less important for performance than the particular set of primitives used to implement the approach.