Heterostructure Bipolar Transistors Research Articles

Secondary ion mass spectrometry quantification: Do you remember when a factor of 2 was good enough?

Well, do you remember when a factor of 2 was good enough? Probably, not unless you have been around secondary ion mass spectrometry (SIMS) since the early 1960s, like one of us has been. This paper will give many references back to the early days of quantification when a local thermal equilibrium model was used to obtain the first results that were accurate to within a factor of 2, but only 60% of the time. It only worked for bulk silicate matrixes. People were not even using SIMS on semiconductors in those days. Several early references showing profiles of ion implants in Si will be referenced, but it was not until 1980 that the first paper was published that explicitly showed how to use ion implants as SIMS standards. People were using ion implants as standards before 1980, but only in limited cases, and with no formal published equations specifying how to use them. But, the samples for which ion implants were used as standards were for dilute concentrations in a single matrix, which had a uniform matrix composition with depth. The rest of the paper will show how we at Eurofins EAG Laboratories tackled the problem of quantification of both major and minor elements in nonuniform, multi-element matrices with continuously graded composition changes using point-by-point CORrected-SIMS. These include SiGe heterostructure bipolar transistors, AlGaAs vertical cavity surface emitting lasers, and B plasma-implanted poly-silicon gates.

Г-L intervalley separation and electron mobility in GaAsSb grown on InP: Transport comparison with the GaInAs and GaInAsSb alloys

GaAs0.51Sb0.49 is lattice-matched to InP and finds electron transport applications in base or absorber layers in high-speed heterostructure bipolar transistors or photodiodes, because its staggered (“type-II”) band alignment with InP favors electron injection across abrupt heterojunctions. Little remains known about electron transport properties and band structure details of GaAsxSb1−x near x = 0.5. Particularly, based on the Γ-L intervalley separation in binary constituents (ΔΓL = 84 meV in GaSb and 290 meV in GaAs at 300 K), interpolation suggests a low Γ-L separation in GaAs0.51Sb0.49 before considering energy gap bowing effects. To gain insight into electron transport in GaAs0.51Sb0.49, we characterized experimental Hall electron mobilities vs carrier concentration at 300 and 77 K in n-type GaAs0.51Sb0.49, Ga0.47In0.53As, and Ga0.76In0.24As0.67Sb0.33 alloys nearly matched to InP. In marked contrast to the other two alloys, GaAs0.51Sb0.49 exhibits a sharp rise in 77 K electron mobility, which evidences L-valley de-population for lower electron concentrations. A two-band transport analysis reveals a Γ-L valley separation ΔΓL = 91 meV at 77 K, significantly lower than values recommended in the literature. Based on the reported temperature variations of ΔΓL in GaAs and GaSb, 84 < ΔΓL < 95 meV is expected at 300 K. The corresponding GaAsxSb1−x L-valley bowing parameter is cL = 1.63 eV, significantly higher than the 1.1–1.2 eV recommended in the literature. In contrast to GaAsxSb1−x, GaInAsSb grown on InP displays a strong alloy scattering, which limits its low-temperature electron mobility.

Mixed-Mode Stress in Silicon–Germanium Heterostructure Bipolar Transistors: Insights From Experiments and Simulations

Recently, a wide class of market segments (e.g., health, material science, security, and communications) is tackled by circuits fabricated in BiCMOS technology, integrating silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) and passives. Currently, the reliability of SiGe HBT devices is a major concern, and much attention is given to self-heating (SH), that limits device performance and regulates their degradation during stress. Moreover, its relevance is supposed to increase with device scaling. In this paper, we explore the reliability issues of SiGe HBTs by combining dedicated experiments and TCAD simulations. We develop and calibrate a TCAD model that is then used to investigate SH effects in both operating and stress conditions. Results show the important role played by the back-end-of-line (BEOL) and by the substrate thermal resistance in dissipating the heat generated by impact ionization. The location at which defects are generated during stress and the microscopic properties of the defects are determined experimentally by means of dedicated noise measurements. Including defects in the TCAD model allows reproducing the degradation observed in stress experiments. Simulations of the SH effects on a stressed device in measurement conditions revealed the presence of a hole hot spot that suggests a possible physical mechanism involved in the degradation slowdown at long stress times reported in the literature.

Transferred-Substrate InP/GaAsSb Heterojunction Bipolar Transistor Technology With <inline-formula> <tex-math notation="LaTeX">${f}_{\text{max}}$ </tex-math> </inline-formula> ~ 0.53 THz

We report on the realization mymargin of transferred-substrate InP/GaAsSb double heterostructure bipolar transistors in a terahertz monolithic integrated circuit process. Transistors with 0.4- $\mu \text{m}$ -wide single emitters reached unilateral gain cutoff frequencies of around 530 GHz with simultaneous current gain cutoff frequencies above 350 GHz. Extrinsic collector capacitance is effectively reduced in the transfer-substrate process. In combination with the high collector breakdown voltage in the InP/GaAsSb heterobipolar transistor structure of 5 V, this process is amenable to analog power applications at millimeter (mm-wave) and sub-mm-wave frequencies. We demonstrate reliable extraction procedures for unilateral gain and current gain cutoff frequencies.

Structural nonlinear effects in In0.53Ga0.47As/GaAs heterostructure bipolar transistor lasers

The effects of carrier capture on nonlinear gain of In0.53Ga0.47As/GaAs heterostructure bipolar transistor (HBT) lasers have been investigated. Calculations show that the gain of transistor laser (TL) for this structure depends on the parameters such as the initial electron energy, structure size, capture time and pump photon energy.

High-performance InP/InGaAs co-integrated metamorphic heterostructure bipolar and field-effect transistors with pseudomorphic base-emitter spacer and channel layers

In the InP/InGaAs metamorphic co-integrated heterostructure bipolar and field-effect transistors (BiFETs), the field-effect transistor (FET) with pseudomorphic channel layer was stacked on the top of the metamorphic heterostructure bipolar transistor (HBT) with pseudomorphic base–emitter spacer layers. In the FET, a relatively thin as well as heavily doped In0.65Ga0.35As pseudomorphic channel layer between two undoped InP layers was employed to enhance the gate forward operation voltage, drain current, and transconductance, simultaneously. On the other hand, after removing the top four layers of material structures, the studied HBT was fabricated on the metamorphic buffer layer. In the metamorphic HBT, the valence band discontinuity at InP/In0.65Ga0.35As heterojunction and emitter injection efficiency could be further extended than the conventional InP/In0.53Ga0.47As lattice-matched HBTs. Furthermore, the delta doping layer between two In0.65Ga0.35As spacer layers at emitter side could effectively eliminate the potential spike at base–emitter junction for reducing the collector–emitter offset voltage. Consequently, the co-integrated metamorphic devices show a good potential for mixed signal integrated circuits and systems applications.

Heterostructures for Optoelectronics: History and Modern Trends

Semiconductor revolution of the 20th century determined not only technological, but also social development of the modern society. The precursors of modern semiconductor electronics were Oleg Losev's discoveries of “crystadine” and “light-emitting diode (LED)” nearly 100 years ago. Creation of the transistor and semiconductor laser and LED based on the homo p-n structure became the most decisive step. Semiconductor optoelectronics was born with the creation of GaAs and GaAsP lasers and “LED.” The possibility to control the type and level of conductivity and injection in p-n junctions was the seed from which semiconductor electronics developed. Heterostructures-“man-made crystals”-solved a more general problem: the necessity to control electron and photon fluxes in crystals. The development of physics and technology for semiconductor heterostructures resulted in drastic changes in our everyday life. It is hardly possible to imagine our recent life without double-heterostructure (DH) laser-based telecommunication systems, without efficient DH LEDs, heterostructure bipolar transistors, and high electron mobility transistors (HEMTs) for high-frequency applications. DH lasers were introduced in every household with CD players. Heterostructure solar cells have been widely used for space and terrestrial applications. The first proposals for heterostructures in semiconductor devices were made as early as in the 1950s, but the most important experimental results were received at the end of the 1960s when the first ideal AlGaAs heterostructures and low threshold room-temperature lasers, efficient heterostructure LEDs, and solar cells were created. Later semiconductor heterostructure became laboratories of low-dimension electron gases. Molecular-beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD) technologies were the basis for the development of new structures, including superlattices, and for the industrial production of a large family of heterostructure semiconductor devices. Quantum dot (QD)-based optoelectronics as a modern trend in optoelectronics is the subject of a more detailed consideration.

A THz InGaAs/InP double heterojunction bipolar transistor with fmax = 325 GHz and BVCBO = 10.6 V

A common-base four finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and fabricated using triple mesa structure and planarization technology. All processes are on 3-inch wafers. The area of each emitter finger is 1 × 15 μm2. The maximum oscillation frequency (fmax) is 325 GHz and the breakdown voltage BVCBO is 10.6 V, which are to our knowledge both the highest fmax and BVCBO ever reported for InGaAs/InP DHBTs in China. The high speed InGaAs/InP DHBT with a high breakdown voltage is promising for submillimeter-wave and THz electronics.

Correction methods of the electrothermal coupling in analog blocks based on heterostructure bipolar transistors

The problem of taking into account the thermal processes in high-performance microcircuits based on heterostructural bipolar transistors (HBT) is considered. A new thermal model of the HBT is suggested, which differs from the known BJT504t model by the addition of thermal resistance and thermal capacity. The means to decrease the thermal resistance of the HBT and to correct the electrothermal coupling in the comparator are suggested. Simulation of the comparator using the simplified model of the transistor in a wide temperature range showed that the use of compensation makes it possible to attain a decrease in the magnitude of hysteresis by a factor of 10.

Passivation of InP heterojunction bipolar transistors by strain controlled plasma assisted electron beam evaporated hafnium oxide

We present structural, stress, and electrical properties of plasma assisted e-beam evaporated hafnium dioxide (HfO2) layers on n-type InP substrates. These layers have subsequently been used for surface passivation of InGaAs/InP heterostructure bipolar transistors either alone or in combination with plasma enhanced chemical vapor deposited SiO2 layers. The use of stacked HfO2/SiO2 results in better interface quality with InGaAs/InP heterostructures, as illustrated by smaller leakage current and improved breakdown voltage. These improvements can be attributed to the reduced defect density and charge trapping at the dielectric-semiconductor interface. The deposition at room temperature makes these films suitable for sensitive devices.

Hafnium oxide passivation of InGaAs/InP heterostructure bipolar transistors by electron beam evaporation

AbstractIn this contribution, we investigate the passivation of InGaAs/InP heterostructures using plasma assisted e‐beam evaporated hafnium oxide (HfO2). The microstructure and optical properties of the HfO2 layers are first examined by X‐ray reflectivity and spectroscopic ellipsometry on Si substrates. The current gain and breakdown voltage of InGaAs/InP heterostructure bipolar transistors (HBTs) have subsequently been used to evaluate the impact and efficiency of the e‐beam evaporated HfO2 passivation layers. The results from these structures have been contrasted with data from similar samples encapsulated with SiO2 using conventional plasma enhanced chemical vapor deposition. The HfO2 passivated InGaAs/InP HBTs show comparable current gains as compared to unpassivated structures. More importantly, in contrast to SiO2‐PECVD devices, the common emitter characteristics of HfO2 passivated HBTs show no degradation in device breakdown voltage. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Study of Metamorphic Co-Integrated Heterostructure Bipolar and Field-Effect Transistors (BiFETs)

DC performance of InP/InGaAs co-integrated metamorphic semiconductor devices grown on GaAs substrate by combining heterostructure bipolar and field-effect transistors (BiFETs) is first demonstrated. In the metamorphic co-integrated BiFETs, the field-effect transistor is stacked on the top of the metamorphic heterostructure bipolar transistor (HBT). For the HBT, the potential spike at base-emitter junction is effectively eliminated for reducing the collector-emitter offset voltage by lowering the energy band at emitter side. A maximum current gain of 255 and a low offset voltage of 105 mV are obtained. Furthermore, with respect to the field-effect transistor, the thin InGaAs channel between two undoped InP layers is heavily doped and two-dimensional electron gas is formed in the channel. An extrinsic transconductance of 265 mS/mm and a saturation current density of 281 mA/mm are achieved.

Surface Passivation of InGaAs/InP HBTs Using Atomic Layer Deposited Al2O3

In this contribution, we investigate the Al2O3 surface passivation of InGaAs/InP heterostructures using thermal atomic layer deposition (ALD) with water vapor, and plasma ALD with oxygen plasma. The microstructure and optical properties of the Al2O3 layers are examined by X-ray reflectivity (XRR) and spectroscopic ellipsometry (SE) on InGaAs/InP epilayers and Si substrates. The dc current gain and breakdown voltage of InGaAs/InP heterostructure bipolar transistors (HBTs) have subsequently been used to evaluate the impact and efficiency of the ALD-Al2O3 passivation layers. The thermal-ALD-Al2O3 passivated InGaAs/InP HBTs show relatively higher current gains as compared to structures passivated using the plasma-ALD process, suggesting differences in the dielectric-semiconductor interface properties. The common emitter characteristics of both (thermal and plasma) ALD-Al2O3 passivated HBTs show, however, fairly comparable device breakdown voltages. These results will be contrasted with results from similar samples passivated with SiO2 using conventional plasma enhanced chemical vapor deposition (PECVD).

Electrical Measurement of the Thermal Impedance of Bipolar Transistors

In this letter, we present a characterization method for the determination of the thermal impedance of heterostructure bipolar transistors. The thermal impedance was characterized using low-frequency S-parameter measurements. We will show that our method can be used to characterize the thermal impedance independent of the transistor size.

Dual approach for bipolar transistor thermal impedance determination

This paper presents a dual approach for a coherent determination and validation of heterostructure bipolar transistor (HBT) thermal impedance. This study relies both on an experimental characterization method and a 3D finite element simulation approach. One section reminds briefly the experimental approach. Another describes the 3D device modeling used for the physics-based thermal simulation. Thereafter, details on the reduction method used for the numerical computation of the thermal impedance are given. As complement to pure thermal simulation, an electrothermal distributed model is proposed and gives an interpretation of the distributed effects in multi-finger devices.

Composite-Collector InGaAs/InP Double Heterostructure Bipolar Transistors with Current-Gain Cutoff Frequency of 242 GHz

To eliminate the conduction band spike at the base-collector interface, an InP/InGaAs double heterostructure bipolar transistor (DHBT) with an InGaAsP composite collector is designed and fabricated using the conventional mesa structure. The DHBT with emitter area of 1.6 × 15 μm2 exhibits current-gain cutoff frequency ft = 242 GHz at the high collector current density Jc = 2.1 mA/μm2, which is to our knowledge the highest ft reported for the mesa InP DHBT in China. The breakdown voltage in common-emitter configuration is more than 5 V. The high-speed InP/InGaAs DHBT with high current density is very suitable for the application in ultra high-speed digital circuits.

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1×15μm2. The breakdown voltage was more than 7V, the current could be more than 100mA. The maximum output power can be more than 80mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305GHz at IC=50mA and VCB=1.5V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.

High Current Multi-finger InGaAs/InP Double Heterojunction Bipolar Transistor with the Maximum Oscillation Frequency 253 GHz

A four-finger InGaAs/InP double heterojunction bipolar transistor is designed and fabricated successfully by using planarization technology. The emitter area of each finger is 1 × 15μm2. The breakdown voltage is more than 7 V, the maximum collector current could be more than 100 mA. The current gain cutoff frequency is as high as 155 GHz and the maximum oscillation frequency reaches 253 GHz. The heterostructure bipolar transistor can offer more than 70mW class-A maximum output power at W band and the maximum power density can be as high as 1.2W/mm.

High-Speed InGaAs/InP Double Heterostructure Bipolar Transistor with High Breakdown Voltage

We design and fabricate an InGaAs/InP double heterostructure bipolar transistor (DHBT). The spike of the conduction band discontinuity between InGaAs base and InP collector is successfully eliminated by insertion of an InGaAs layer and two InGaAsP layers. The current gain cutoff frequency and maximum oscillation frequency are as high as 155 and 144 GHz. The breakdown voltage in common-emitter configuration is more than 7 V. The high cutoff frequency and high breakdown voltage make high-speed and high-power circuits possible.