Heterogeneous Threads Research Articles

MM-LMF: A Low-Rank Multimodal Fusion Dangerous Driving Behavior Recognition Method Based on FMCW Signals

Multimodal research is an emerging field of artificial intelligence, and the analysis of dangerous driving behavior is one of the main application scenarios in the field of multimodal fusion. Aiming at the problem of data heterogeneity in the process of behavior classification by multimodal fusion, this paper proposes a low-rank multimodal data fusion method, which utilizes the complementarity between data modalities of different dimensions in order to classify and identify dangerous driving behaviors. This method uses tensor difference matrix data to force low-rank fusion representation, improves the verification efficiency of dangerous driving behaviors through multi-level abstract tensor representation, and solves the problem of output data complexity. A recurrent network based on the attention mechanism, AR-GRU, updates the network input parameter state and learns the weight parameters through its gated structure. This model improves the dynamic connection between modalities on heterogeneous threads and reduces computational complexity. Under low-rank conditions, it can quickly and accurately classify and identify dangerous driving behaviors and give early warnings. Through a large number of experiments, the accuracy of this method is improved by an average of 1.76% compared with the BiLSTM method and the BiGRU-IAAN method in the training and verification of the self-built dataset.

Kinetics of ionic liquid-facilitated cellulose decrystallization by Raman spectral mapping

The decrease in crystallinity of a cotton thread upon exposure to the ionic liquid 1-ethyl-3-methylimidazolium acetate is investigated via two-dimensional Raman spectral mapping of the thread cross-section. By monitoring an intrinsic cellulose I Raman mode, the transition from highly crystalline cellulose I to amorphous cellulose is monitored as a function of treatment time and temperature. At extended treatment times, a heterogeneous decrystallization occurs where only those fibers at the outer edge of the thread decrystallize and dissolve while fibers in the thread center exhibit a constant crystallinity. As a result, a large amorphous cellulose shell develops which surrounds a central bundle of still-distinct and highly crystalline cotton fibers. Observed trends in the temperature-dependent rate of heterogeneous thread decrystallization are attributed to a transition to diffusion-limited decrystallization associated with the development of a solvent-swollen amorphous polymer layer. Raman spectral mapping provides new opportunities to investigate the effect of treatment conditions on the spatial extent and degree of crystallinity as well as the mechanism of decrystallization in cellulose biopolymer materials.

Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale.

With the end of CPU core scaling due to dark silicon limitations, customized accelerators on FPGAs have gained increased attention in modern datacenters due to their lower power, high performance and energy efficiency. Evidenced by Microsoft's FPGA deployment in its Bing search engine and Intel's 16.7 billion acquisition of Altera, integrating FPGAs into datacenters is considered one of the most promising approaches to sustain future datacenter growth. However, it is quite challenging for existing big data computing systems-like Apache Spark and Hadoop-to access the performance and energy benefits of FPGA accelerators. In this paper we design and implement Blaze to provide programming and runtime support for enabling easy and efficient deployments of FPGA accelerators in datacenters. In particular, Blaze abstracts FPGA accelerators as a service (FaaS) and provides a set of clean programming APIs for big data processing applications to easily utilize those accelerators. Our Blaze runtime implements an FaaS framework to efficiently share FPGA accelerators among multiple heterogeneous threads on a single node, and extends Hadoop YARN with accelerator-centric scheduling to efficiently share them among multiple computing tasks in the cluster. Experimental results using four representative big data applications demonstrate that Blaze greatly reduces the programming efforts to access FPGA accelerators in systems like Apache Spark and YARN, and improves the system throughput by 1.7 × to 3× (and energy efficiency by 1.5× to 2.7×) compared to a conventional CPU-only cluster.

Fiber composite slices for multiplexed immunoassays.

Fabrication methods for the development of multiplexed immunoassay platforms primarily depend on the individual functionalization of reaction chambers to achieve a heterogeneous reacting substrate composition, which increases the overall manufacturing time and cost. Here, we describe a new type of low-cost fabrication method for a scalable immunoassay platform based on cotton threads. The manufacturing process involves the fabrication of functionalized fibers and the arrangement of these fibers into a bundle; this bundle is then sectioned to make microarray-like particles with a predefined surface architecture. With these sections, composed of heterogeneous thread fragments with different types of antibodies, we demonstrated quantitative and 7-plex immunoassays. We expect that this methodology will prove to be a versatile, low-cost, and highly scalable method for the fabrication of multiplexed bioassay platforms.

Determination of strength properties of sewing seams in technical articles produced by combined sewing threads

The results of study of strength properties of sewing seams in technical articles produced by special-purpose combined sewing threads are presented. Tests demonstrated that the nature of seam disruption depends on the physicomechanical properties of both the sewing threads and the materials being sewed as well as on the way the specimens are made and tested. It is shown that the seams created by using heterogeneous sewing threads meet the requirements set for use of the technical articles.

Compiler-Supported Thread Management for Multithreaded Network Processors

Traditionally, runtime management involving CPU sharing, real-time scheduling, etc., is provided by the runtime environment (typically an operating system) using hardware support such as timers and interrupts. However, due to stringent performance requirements on network processors, neither OS nor hardware mechanisms are typically feasible/available. Mapping packet processing tasks on network processors involves complex trade-offs to maximize parallelism and pipelining. Due to an increase in the size of the code store and complexity of application requirements, network processors are being programmed with heterogeneous threads that may execute code belonging to different tasks on a given micro-engine. Also, most network applications are streaming applications that are typically processed in a pipelined fashion. Thus, the tasks on different micro-engines are pipelined in such a way as to maximize the throughput. Tasks themselves could have different runtime performance demands. In this article, we focus on network processors on which hardware can only schedule threads in a round-robin fashion and no OS assistance is provided. We show that it is very difficult and inefficient for the programmer to meet the constraints of runtime management by coding them statically. Due to the infeasibility of hardware or OS solution (even in the near future), we undertake a compiler approach. We propose a complete compiler solution to automatically insert explicit context switch (ctx) instructions provided on the network processor such that the execution of threads is better manipulated at runtime to meet their constraints. Two approaches are presented that can control programs’ runtime behavior with different applicability and overheads. We show that it is feasible and also opens new application domains that would need heterogeneous thread programming. Such approaches would in general become important for multicore processors. Finally, our experiments show that the runtime constraints are enforced nearly ideally with minimal runtime degradation and small code growth.

Bothnia

In this paper, we introduce Bothnia, an extension to the Intel production graphics driver to support a shared virtual memory heterogeneous multithreading programming model. With Bothnia, the Intel graphics device driver can support both the traditional 3D graphics rendering software stack and a new class of heterogeneous multithreaded applications, which can use both IA (Intel Architecture) CPU cores and Intel integrated Graphics and Media Accelerator (GMA) cores in the same virtual address space. We describe the necessary architectural supports in both IA CPU and the GMA cores and present a reference Bothnia implementation. For a set of GPU accelerated media applications on a PC platform with Intel Core 2 Duo CPU and the Intel integrated GMA X3000 running under the Windows XP operating system, Bothnia achieves an average speedup of 3.6x compared to using the GPU as a device, primarily due to Bothnia's support for creation of shared virtual address space between heterogeneous threads of the same application spread on both IA CPU and GMA cores.

The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor

As CMOS feature sizes continue to shrink and traditional microarchitectural methods for delivering high performance (e.g., deep pipelining) become too expensive and power-hungry, chip multiprocessors (CMPs) become an exciting new direction by which system designers can deliver increased performance. Exploiting parallelism in such designs is the key to high performance, and we find that parallelism must be exploited at multiple levels of the system: the thread-level parallelism that has become popular in many designs fails to exploit all the levels of available parallelism in many workloads for CMP systems. We describe the Cell Broadband Engine and the multiple levels at which its architecture exploits parallelism: data-level, instruction-level, thread-level, memory-level, and compute-transfer parallelism. By taking advantage of opportunities at all levels of the system, this CMP revolutionizes parallel architectures to deliver previously unattained levels of single chip performance. We describe how the heterogeneous cores allow to achieve this performance by parallelizing and offloading computation intensive application code onto the Synergistic Processor Element (SPE) cores using a heterogeneous thread model with SPEs. We also give an example of scheduling code to be memory latency tolerant using software pipelining techniques in the SPE.

Effective thread management on network processors with compiler analysis

Mapping packet processing tasks on network processor micro-engines involves complex tradeoffs that relating to maximizing parallelism and pipelining. Due to an increase in the size of the code store and complexity of the application requirements, network processors are being programmed with heterogeneous threads that may execute code belonging to different tasks on a given micro-engine. Also, most network applications are streaming applications that are typically processed in a pipelined fashion. Thus, the tasks on different micro-engines are pipelined in such a way as to maximize the throughput. Tasks themselves could have different run time performance demands. Traditionally, runtime management involving processor sharing, real-time scheduling etc. is provided by the runtime environment (typically an operating system) using the hardware support for timers and interrupts that allows time slicing the resource amongst the tasks. However, due to stringent performance requirements on network processors (which process packets from very high speed network traffic), neither OS nor hardware mechanisms are typically feasible/available.In this paper, we show that it is very difficult and inefficient for the programmer to meet the constraints of runtime management by coding them statically. Due to the infeasibility of hardware or OS solution (even in the near future), the only choice left is a compiler approach.We propose a complete compiler solution to automatically insert explicit context switch (ctx) instructions provided on the processors so that the execution of programs is better manipulated at runtime to meet their constraints. We show that such an approach is feasible opening new application domains that would need heterogeneous thread programming. Such approaches would in general become important for multi-core processors.

Arachne: a portable threads system supporting migrant threads on heterogeneous network farms

We present the design and implementation of Arachne, a threads system that can be interfaced with a communications library for multithreaded distributed computations. In particular, Arachne supports thread migration between heterogeneous platforms, dynamic stack size management, and recursive thread functions. Arachne is efficient, flexible, and portable-it is based entirely on C and C++. To facilitate heterogeneous thread operations, we have added three keywords to the C++ language. The Arachne preprocessor takes as input code written in that language and outputs C++ code suitable for compilation with a conventional C++ compiler. The Arachne runtime system manages all threads during program execution. We present some performance measurements on the costs of basic thread operations and thread migration in Arachne and compare these to costs in other threads systems.

“Good Try, Mr. Paul”: Populism and the Politics of African Land Use

These people and movements, then, are populist and have much in common: the Levellers, the Diggers, the Chartists, the Narodniki, the US populists … Gandi… Nyerere. The list is very long but still very incomplete.Reading Paul Richards's excellent paper and, most particularly, the set of international commentaries has been something of a salutary experience and, as I have now discovered, has made my task wholly unenviable. There is, of course, something here for everyone as one might anticipate in any state of the art paper of this scope. The respondents' remarks alone cover a huge intellectual terrain from epistemology to animal traction, from bibliographic style to Shakespearean metaphor, and a good deal more. It is difficult to know what to make of all this let alone to weave these heterogeneous threads into a pleasing, coherent tapestry. Yet, beneath this patina of diversity, lie much more deep seated interpretative and theoretical differences that are intriguing in their own right. For example, Richards's plea for the “honest face” of particularism in relation to what he posits as a congenital drift toward arid and sterile global abstractions and grand universal theory was lent wildly different interpretations by his erstwhile critics. For some this was a glorious new mandate to return to Gluckman and some forms of nineteenth century anthropology; for others it was a disastrous slide into the primal cess-poll of crude empiricism, Boasian salmon recipes, and rampant particularism. For others it represented a healthy appraisal of “the great range of specificities that one should be prepared to confront within a (Marxist) framework” (Henry Bernstein). And all this is wrapped in the almost inevitable empirical provincialism of “my village” or “my region” which provide the basis of individual scepticism and conceptual disproof. Because this is the case, my remarks make no pretense to be either a grand synthesis of highly contradictory contributions or a Herculean effort to locate a "common ground" as some of the comments at the panel discussion opined. In my opinion neither are possible.