Heterogeneous Multiprocessor Architecture Research Articles

Scheduling analysis and correction for dependent real-time tasks upon heterogeneous multiprocessor architectures

Scheduling analysis and correction for dependent real-time tasks upon heterogeneous multiprocessor architectures

Scheduling energy consumption-constrained workflows in heterogeneous multi-processor embedded systems

Heterogeneous multi-processor architecture which achieves rich functionalities with different types of processors, is widely used to provide powerful calculating capability while keeping energy consumption under control. Although this architecture can improve system flexibility for adapting to future requirement variations, it results in a complex multi-task scheduling problem for system designers to produce a reasonable schedule that satisfies all deadline, data dependency, and energy limitation constraints. In this paper, we concentrate on the energy consumption-constrained scheduling problem of workflows in heterogeneous multi-processor embedded systems. First, we model the workflows and energy consumption of processors, and formulate the energy consumption-constrained scheduling problem as an optimization one whose objective is to shorten the schedule length of workflows as much as possible. Then, with an improved energy per-assignment strategy, we propose a novel energy difference coefficient-based scheduling algorithm to produce an approximately optimal allocation of processors, frequencies, and start times for each task while guaranteeing that the data dependency and energy limitation constraints are satisfied. Finally, experiments on both randomly-generated and real-world workflows are conducted to verify the reliability and efficiency of the proposed approach.

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

Programming heterogeneous multiprocessor architectures combining multiple processor cores and hardware accelerators is a real challenge. Computer-aided design and development tools try to reduce the large design space by simplifying hardware-software mapping mechanisms. However, energy consumption is not well supported in most of design space exploration methodologies due to the difficulty to estimate energy consumption fast and accurately. To this aim, this paper proposes and validates an exploration method for partitioning tilling-based parallel applications on software cores and hardware accelerators under energy-efficiency constraints. The methodology is based on energy and performance measurement of a tiny subset of the design space and an analytical formulation of the performance and energy of an application kernel mapped onto a heterogeneous architecture. This closed-form expression is captured and solved using Mixed Integer Linear Programming, which allows for very fast exploration and results in the best hardware and software partitioning under energy constraint. The approach is validated on two application kernels using a Zynq-based architecture showing more than 12% acceleration speed-up and energy saving compared to standard approaches. Results also show that the most energy-efficient solution is application- and platform-dependent and moreover hardly predictable, which highlights the need for fast exploration tools as in this paper.

SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems

This work faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototype SystemC-based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper.

Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems

With the advent of heterogeneous multiprocessor architectures, efficient scheduling for high performance has been of significant importance. However, joint considerations of reliability, temperature, and stochastic characteristics of precedence-constrained tasks for performance optimization make task scheduling particularly challenging. In this paper, we tackle this challenge by using an affinity (i.e., probability)-driven task allocation and scheduling approach that decouples schedule lengths and thermal profiles of processors. Specifically, we separately model the affinity of a task for processors with respect to schedule lengths and the affinity of a task for processors with regard to chip thermal profiles considering task reliability and stochastic characteristics of task execution time and intertask communication time. Subsequently, we combine the two types of affinities, and design a scheduling heuristic that assigns a task to the processor with the highest joint affinity. Extensive simulations based on randomly generated stochastic and real-world applications are performed to validate the effectiveness of the proposed approach. Experiment results show that the proposed scheme can reduce the system makespan by up to 30.1% without violating the temperature and reliability constraints compared to benchmarking methods.

Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture

Single-instruction set architecture (ISA) heterogeneous multi-processor architecture is promising for developing multi-processor system-on-chips (MPSoCs). In this architecture, all processors execute the same instruction set, yet with various performance and power behavior, since processors may have various micro-architectures. Therefore, systems with this architecture have the advantages of easy to develop new functions as the homogeneous architecture, and easy to customize the resource allocation to achieve high energy efficiency as the heterogeneous architecture. However, for an MPSoC utilizing the target architecture, a key design issue is how to select the set of processors so that the target system can achieve good performance while the cost of the chip is constrained to the expected value. To solve this, in this paper, we propose a processor allocation method for MPSoCs with single-ISA heterogeneous multi-core architecture. The goal of the proposed method is to automatically synthesize the allocation of cores for the given workload so that the performance is optimized while the resource constraint is met. To the best of our knowledge, this is the first work that tackles the processor allocation problem for MPSoCs with the target architecture. To bring out the best performance of a hardware configuration, the proposed algorithm also synthesizes the software design of task mapping for a selected hardware configuration. The experimental results show that, compared with the homogeneous architecture with the least cost and lowest performance cores only, even if the number of core is set to the maximum parallelism degree of the target workload, the proposed method achieves up to 8.25% of performance improvement among all the cases we evaluated while the area constraint is met. Compared with the architecture with all high performance but large cores, when the number of cores is also set to the same as the maximum parallelism degree of the target workload, the proposed method has at most 11.5% of performance degradation, while the area cost is reduced by 60.7%.

TBES

This article describes TBES, a software end-to-end environment for synthesizing multitask applications on FPGAs. The implementation follows a template-based approach for creating heterogeneous multiprocessor architectures. Heterogeneity stems from the use of general-purpose processors along with custom accelerators. Experimental results demonstrate substantial speedup for several classes of applications. Furthermore, this work allows for reducing development costs and saving development time for the software architect, the domain expert, and the optimization expert. This work provides a framework to bring together various existing tools and optimisation algorithms. The advantages are manifold: modularity and flexibility, easy customization for best-fit algorithm selection, durability and evolution over time, and legacy preservation including domain experts' know-how. In addition to the use of architecture templates for the overall system, a second contribution lies in using high-level synthesis for promoting exploration of hardware IPs. The domain expert, who best knows which tasks are good candidates for hardware implementation, selects parts of the initial application to be potentially synthesized as dedicated accelerators. As a consequence, the HLS general problem turns into a constrained and more tractable issue, and automation capabilities eliminate the need for tedious and error-prone manual processes during domain space exploration. The automation only takes place once the application has been broken down into concurrent tasks by the designer, who can then drive the synthesis process with a set of parameters provided by TBES to balance tradeoffs between optimization efforts and quality of results. The approach is demonstrated step by step up to FPGA implementations and executions with an MJPEG benchmark and a complex Viola-Jones face detection application. We show that TBES allows one to achieve results with up to 10 times speedup to reduce development times and to widen design space exploration.

EDZL Scheduling and Schedulability Analysis for Performance Asymmetric Multiprocessors

Heterogeneous multiprocessor architectures allow embedded real-time systems to better match computing resources to each application's needs and dynamic workload requirements, thereby providing many opportunities for improved performance with reduced power consumption. Unfortunately, guaranteeing real-time requirements on heterogeneous multiprocessors remains a critical problem due to the lack of appropriate scheduling algorithms and analysis methods. In this paper, we consider EDZL (Earliest Deadline First until Zero-Laxity) for performance asymmetric multiprocessor scheduling. EDZL has been shown to outperform other scheduling policies such as global EDF on identical multiprocessors. We show that EDZL is still effective on performance asymmetric multi-processors, and present an efficient EDZL schedulability test. Experimental results show that EDZL scheduling is able to schedule up to 20% more task sets than global EDF and that our new EDZL schedulability test can accept up to 30% more schedulable task sets than a presently exiting one.

Heuristics on Reachability Trees for Bicriteria Scheduling of Stream Graphs on Heterogeneous Multiprocessor Architectures

In this article, we partition and schedule Synchronous Dataflow (SDF) graphs onto heterogeneous execution architectures in such a way as to minimize energy consumption and maximize throughput. Partitioning and scheduling SDF graphs onto homogeneous architectures is a well-known NP-hard problem. The heterogeneity of the execution architecture makes our problem exponentially challenging to solve. We model the problem as a weighted sum and solve it using novel state space exploration inspired from the theory of parallel automata. The resultant heuristic algorithm results in good scheduling when implemented in an existing stream framework.

Emulation and Analytical Model of PIM Supplemental Computing Element via HDL

Abstract This article presents and describes the simulation and emulation of single processing core, designed for new heterogeneous multiprocessor computer architectures with supplemental computing elements in the operating memory. We study the emulated results over the simulated model to confirm it’s usability in the overall simulation of complete system. The simulated models are developed based on existing data, comparing time markers, measuring the output performance against the results from the emulation. Using additional computing elements in the memory will allows us to improve the current limitations of the conventional architectures.

A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures

Today's heterogeneous architectures bring together multiple general-purpose CPUs and multiple domain-specific GPUs and FPGAs to provide dramatic speedup for many applications. However, the challenge lies in utilizing these heterogeneous processors to optimize overall application performance by minimizing workload completion time. Operating system and application development for these systems is in their infancy. In this article, we propose a new scheduling and workload balancing scheme, HDSS, for execution of loops having dependent or independent iterations on heterogeneous multiprocessor systems. The new algorithm dynamically learns the computational power of each processor during an adaptive phase and then schedules the remainder of the workload using a weighted self-scheduling scheme during the completion phase. Different from previous studies, our scheme uniquely considers the runtime effects of block sizes on the performance for heterogeneous multiprocessors. It finds the right trade-off between large and small block sizes to maintain balanced workload while keeping the accelerator utilization at maximum. Our algorithm does not require offline training or architecture-specific parameters. We have evaluated our scheme on two different heterogeneous architectures: AMD 64-core Bulldozer system with nVidia Fermi C2050 GPU and Intel Xeon 32-core SGI Altix 4700 supercomputer with Xilinx Virtex 4 FPGAs. The experimental results show that our new scheduling algorithm can achieve performance improvements up to over 200% when compared to the closest existing load balancing scheme. Our algorithm also achieves full processor utilization with all processors completing at nearly the same time which is significantly better than alternative current approaches.

Basics of virtual machine migration on heterogeneous architectures for self-optimizing mechatronic systems

The combination of virtualization and heterogeneous multi-processor architectures supports the development of efficient platforms for self-optimizing mechatronic systems, which are characterized by varying resource requirements. Virtualization addresses dependability issues and adds runtime flexibility to provide an appropriate resource management. Real-time requirements have to be met and existing real-time virtualization solutions are characterized by a static mapping of virtual machines to processors and do not use the full potential of heterogeneous architectures. The sketched architecture applies migration and emulation to realize a dynamic assignment of virtual machines to processors. This work identifies the necessary conditions for migration and the degree of communication between hypervisor and operating system that is indispensable for migration decisions. System virtualization is an approach of coarse-grained system consolidation, for which reason implementation issues and possibilities to reduce the high overhead are discussed. The implementation of a real-time capable virtual machine migration requires paravirtualization, that is to say a modification of the guest operating systems. The need to modify the guest operating system is outweighed by the advantages in terms of flexibility of an explicit communication and the resulting cooperation of hypervisor and guest operating system.

A System-Level Modeling Methodology for Performance-Driven Component Selection in Multicore Architectures

System complexity, driven by both increasing transistor count and customer need for more and more savvy applications, has increased so dramatically that system design and integration can no longer be an after-thought. With this increasing complexity of the system design, it has become very critical to enhance system design productivity to meet the time-to-market demands and reduce product development cost. Realtime embedded system designers are facing extreme challenges in the underlying architectural design selection. This involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor-system-on-chip platform has set innovative trends for the realtime systems and system-on-chip designers. The consequences of this trend imply a shift in concern from computation and sequential algorithms to modeling concurrency, synchronization, and communication in every aspect of hardware and software codesign and development. Therefore, there is a need for a high level methodology that can provide a complete system modeling and architecture/component selection platform. The proposed six-step system modeling methodology provides a process for performance driven component selection, to avoid costly iterative system design re-spins, thereby enhancing system design productivity. We demonstrate our methodology by applying it onto a network-on-chip architecture for selecting its components given certain system specification and system-level performance requirements.

Accelerating network applications by distributed interfaces on heterogeneous multiprocessor architectures

Hosts with several, possibly heterogeneous and/or multicore, processors provide new challenges and opportunities to accelerate applications with high communications bandwidth requirements. Many opportunities to scale these network applications with the increase in the link bandwidths are related to the exploitation of the available parallelism provided by the presence of several processing cores in the servers, not only for computing the workload of the user application but also for decreasing the overhead associated to the network interface and the system software. This paper analyses some alternatives to distribute the network interface among the different cores available in the host. These alternatives include the use of heterogeneous multicore processors, such as network processors, and the exploitation of the affinity between the network interface and the location (proximity to the memories where the different data structures are stored) and characteristics of the processing architecture. The proposed distributed network interfaces provide improvements in throughput and latency that have been experimentally evaluated by using an intrusion prevention system, which constitutes a useful network function.

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

Today's integrated circuit technologies allow the design of complete systems on a single chip which execute complex applications specified as a set of tasks. The tasks are managed by an Operating System whose main role consists in defining the resource allocation and the temporal scheduling. One of the main characteristics of these architectures is the heterogeneity of their execution resources which makes this scheduling complex. In this paper, we propose a neural network based model for the design of heterogeneous multiprocessor architectures scheduler. Previous works have shown that neural networks using the Hopfield model can be defined to schedule tasks on an homogeneous architecture. This approach was extended to take platform heterogeneity into account. The work presented in this paper is based on a new neural network structure using inhibitor neurons. These neurons allow to limit the number of additional neurons and the number of network re-initialisations to reach convergence. We compare our network to the classic solutions based on the Hopfield neural network. These comparisons show that the number of neurons is reduced by a factor of more than two, which reduces the time convergence. We also compare our approach in terms of number of migrations with the PFair algorithm which is known as an optimal solution in the context of homogeneous architecture. The results show that our solution significantly limit the number of task migrations. Finally, we present results in the context of heterogeneous multiprocessor architectures, which is representative of complex system-on-chip.

Platform-based software design flow for heterogeneous MPSoC

Current multimedia applications demand complex heterogeneous multiprocessor architectures with specific communication infrastructure in order to achieve the required performances. Programming these architectures usually results in writing separate low-level code for the different processors (DSP, microcontroller), implying late global validation of the overall application with the hardware platform. We propose a platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources. We use a high-level environment to capture both application and architecture initial representations. An executable software stack is generated automatically for each processor from the initial model. The software generation and validation is performed gradually corresponding to different software abstraction levels. Specific software development platforms (abstract models of the architecture) are generated and used to allow debugging of the different software components with explicit hardware-software interaction. We applied this approach on a multimedia platform, involving a high performance DSP and a RISC processor, to explore communication architecture and generate an efficient executable code for a multimedia application. Based on automatic tools, the proposed flow increases productivity and preserves design quality.

A rule-based availability-driven cosynthesis scheme

The co-synthesis of hardware---software systems for complex embedded applications has been studied extensively with focus on various qualitative system objectives such as high speed performance and low power dissipation. One of the main challenges in the construction of multiprocessor systems for complex real time applications is provide high levels of system availability that satisfies the users' expectations. Even though the area of hardware software cosynthesis has been studied extensively in the recent past, the issues that specifically relate to design exploration for highly available architectures need to be addressed more systematically and in a manner that supports active user participation. In this paper, we propose a user-centric co-synthesis mechanism for generating gracefully degrading, heterogeneous multiprocessor architectures that fulfills the dual objectives of achieving real-time performance as well as ensuring high levels of system availability at acceptable cost. A flexible interface allows the user to specify rules that effectively capture the users' perceived availability expectations under different working conditions. We propose an algorithm to map these user requirements to the importance attached to the subset of services provided during any functional state. The system availability is evaluated on the basis of these user-driven importance values and a CTMC model of the underlying fail-repair process. We employ a stochastic timing model in which all the relevant performance parameters such as task execution times, data arrival times and data communication times are taken to be random variables. A stochastic scheduling algorithm assigns start and completion time distributions to tasks. A hierarchical genetic algorithm optimizes the selections of resources, i.e. processors and busses, and the task allocations. We report the results of a number of experiments performed with representative task graphs. Analysis shows that the co-synthesis tool we have developed is effectively driven by the user's availability requirements as well as by the topological characteristics of the task graph to yield high quality architectures. We experimentally demonstrate the edge provided by a stochastic timing model in terms of performance assessment, resource utilization, system-availability and cost.

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

A heterogeneous multiprocessor architecture for flexible media processing

Eclipse is a scalable architecture template for designing data-dependent stream-processing subsystems of media-processing SoCs. It combines application configuration flexibility with the efficiency of function-specific coprocessors that concurrently execute the tasks of one or more applications.

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems

The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologiesenable integration of multiple software programmable processors (e.g., CPUs,DSPs) and dedicated hardware components into a single cost-efficient IC. Ourtop-down design methodology with various abstraction levels helps designingthese ICs in a reasonable amount of time. This methodology starts with a high-levelexecutable specification, and converges towards a silicon implementation.A major task in the design process is to ensure that all components (hardwareand software) communicate with each other correctly. In this article, we tacklethis problem in the context of the signal processing domain in two ways: wepropose a modular, flexible, and scalable heterogeneous multi-processor architecturetemplate based on distributed shared memory, and we present an efficient andtransparent protocol for communication and (re)configuration. The protocolimplementations have been incorporated in libraries, which allows quick traversalof the various abstraction levels, so enabling incremental design. The designdecisions to be taken at each abstraction level are evaluated by means of(co-)simulation. Prototyping is used too, to verify the system's functionalcorrectness. The effectiveness of our approach is illustrated by a designcase of a multi-standard video and image codec.