Heterogeneous Multicore Research Articles

Accelerating Image-based Pest Detection on a Heterogeneous Multicore Microcontroller

Accelerating Image-based Pest Detection on a Heterogeneous Multicore Microcontroller

Analysis and Mitigation of Shared Resource Contention on Heterogeneous Multicore: An Industrial Case Study

Analysis and Mitigation of Shared Resource Contention on Heterogeneous Multicore: An Industrial Case Study

Thermal Safe Power Constrained Dynamic Mapping for Heterogeneous Multicore System

Heterogeneous multicore system could provide high flexibility for applications through integrating different types of cores. As the number of cores increases, more and more transistors are integrated which could lead to the rise of chip temperature, thus have a negative impact on the system performance. At present, the typical method to tackle this problem is dynamic voltage and frequency scaling (DVFS) which reduces the voltage and frequency to achieve cooling. However, DVFS will make the heterogeneous multicore system unable to take full advantage of its performance. This paper proposes a dynamic mapping method called TspDM which maximizes the system performance target under the premise of satisfying the temperature safety power. TspDM exploits the runtime performance counters of running threads to dynamically adjust thread mapping. Specifically, a lightweight Artificial Neural Network (ANN) model is proposed to obtain the thread-to-core type mapping when a remapping process is activated. Subsequently, TspDM determines the specific core locations of threads according to the number of threads mapped to a certain core type and the thermal safety power computation. The experimental results show that the proposed method is 21% better than that of PCMig while ensuring the thermal safety of heterogeneous platform. In addition, TspDM outperforms recent performance constrained and power constrained literature in terms of system throughput.

Homogeneous and Heterogeneous Multicore Systems

Multicore systems have gained significant importance in the Automotive industry due to data- intensive applications, such as image processing, high- speed process, and GPS application. It enables manufacturers to build smaller chips, simplifying board architecture and routing, reducing power consumption and cost and increasing programmability. Multicore platforms are segregated into two categories namely Homogeneous (symmetric) and Heterogeneous (asymmetric) multicore systems. In Homogeneous systems, all cores are the same, including frequencies, cache sizes and functions. In Heterogeneous systems, different cores operate with different frequencies, cache sizes and functions. In this paper, we are going to discuss various aspects of homogeneous and heterogeneous multicore architectures like number and level of caches, interconnection of the cores, Physical and Temporal isolation, Energy Efficiency, Concurrency, Performance, Reliability and Robustness along with the evaluation of these two architectures for applications based on the above-mentioned aspects.

Qsmix: Q-learning-based task scheduling approach for mixed-critical applications on heterogeneous multi-cores

Qsmix: Q-learning-based task scheduling approach for mixed-critical applications on heterogeneous multi-cores

Service scheduling strategy for microservice and heterogeneous multi-cores-based edge computing apparatus in smart girds with high renewable energy penetration

The microservice-based smart grid service (SGS) organization and the heterogeneous multi-cores-based computing resource supply are the development direction of edge computing in smart grid with high penetration of renewable energy sources and high market-oriented. However, their application also challenges the service schedule for edge computing apparatus (ECA), the physical carrier of edge computing. In the traditional scheduling strategy of SGS, an SGS usually corresponds to an independent application or component, and the heterogeneous multi-core computing environment is also not considered, making it difficult to cope with the above challenges. In this paper, we propose an SGS scheduling strategy for the ECA. Specifically, we first present an SGS scheduling framework of ECA and give the essential element of meeting SGS scheduling. Then, considering the deadline and importance attributes of the SGS, a microservice scheduling prioritizing module is proposed. On this basis, the inset-based method is used to allocate the microservice task to the heterogeneous multi-cores to utilize computing resources and reduce the service response time efficiently. Furthermore, we design the scheduling unit dividing module to balance the delay requirement between the service with early arrival time and the service with high importance in high concurrency scenarios. An emergency mechanism (EM) is also presented for the timely completion of urgent SGSs. Finally, the effectiveness of the proposed service scheduling strategy is verified in a typical SGS scenario in the smart distribution transformer area.

Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS

Heterogeneous multi-core platforms, such as ARM big.LITTLE are widely used to execute embedded applications under multiple and contradictory constraints, such as energy consumption and real-time execution. To fulfill these constraints and optimize system performance, application tasks should be efficiently mapped on multi-core platforms. Embedded applications are usually tolerant to approximated results but acceptable Quality-of-Service (QoS). Modeling embedded applications by using the elastic task model, namely, Imprecise Computation (IC) task model, can balance system QoS, energy consumption, and real-time performance during task deployment. However, state-of-the-art approaches seldom consider the problem of IC task deployment on heterogeneous multi-core platforms. They typically neglect task migration, which can improve the solutions due to its flexibility during the task deployment process. This paper proposes a novel QoS-aware task deployment method to maximize system QoS under energy and real-time constraints, where frequency assignment, task allocation, scheduling, and migration are optimized simultaneously. The task deployment problem is formulated as mixed-integer non-linear programming. Then, it is linearized to mixed-integer linear programming to find the optimal solution. Furthermore, based on problem structure and problem decomposition, we propose a novel heuristic with low computational complexity. The sub-problems regarding frequency assignment, task allocation, scheduling, and adjustment are considered and solved in sequence. Finally, the simulation results show that the proposed task deployment method improves the system QoS by 31.2% on average (up to 112.8%) compared to the state-of-the-art methods and the designed heuristic achieves about 53.9% (on average) performance of the optimal solution with a negligible computing time.

Type-Aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms

To utilize the performance benefits of heterogeneous multicore platforms in real-time systems, we need task models that expose the parallelism and heterogeneity of the workload, such as typed DAG tasks, as well as scheduling algorithms that effectively exploit this information. In this paper, we introduce <i>type-aware federated scheduling</i> algorithms for sporadic typed DAG tasks with implicit deadlines running on a heterogeneous multicore platform with two different types of cores. In type-aware federated scheduling, a task can be executed in one of the three strategies: <i>Exclusive Allocation</i>, <i>Semi-Exclusive Allocation</i>, and <i>Sequential and Share</i>. In <i>Exclusive Allocation</i>, clusters of cores of both core types are exclusively allocated to tasks, while cores of only one type are exclusively allocated to tasks in <i>Semi-Exclusive Allocation</i>. The workload of the other type from tasks in <i>Semi-Exclusive Allocation</i> and the workload from tasks in <i>Sequential and Share</i> share the cores that are not exclusively allocated to any task. We prove that our type-aware federated scheduling algorithm has a capacity augmentation bound of 7.25. We also show that no constant capacity augmentation bound can be obtained without <i>Semi-Exclusive Allocation</i>. Compared to the state of the art, the type-aware federated scheduling algorithm achieves better schedulability, especially for task sets with skewed workload.

MRCN: Throughput-Oriented Multicast Routing for Customized Network-on-Chips

The relentless proliferation of Big Data and artificial intelligence has compelled computing platform architectures to evolve into heterogeneous multicores for greater energy efficiency. A customized network-on-chip (NoC) supporting interconnection diversity is pivotal for the asymmetric data-access traffic requirements of modern heterogeneous multicore system-on-chip (SoC). A significant portion of on-chip data access comprises single-source multi-destination (SSMD) traffic, which supports barrier synchronization, multi-threading, cache coherency protocols, and deep neural network (DNN) acceleration. By amortizing SSMD traffic, multicast routing is essential for effectively utilizing communication bandwidth. One of the primary concerns in supporting multicast routing in NoCs is to circumvent the additional deadlock conditions caused by branch operations among the active routers. However, it is challenging to implement the throughput-optimized multicast routing in irregular topology-based NoCs because the deadlock conditions become highly complicated, and the Hamiltonian path required to apply the labeling rule may not exist. Two important observations were identified regarding multicast routing in customized NoCs: 1) Even if the NoC lacks a Hamiltonian path, deadlock-freedom can be guaranteed by restricting branch operations to a specific destination. 2) A variable path diversity in a custom topology can be leveraged in routing path allocation and branch. Based on these properties, this study proposes a deadlock-free and throughput-enhanced multicast routing for customized NoC (MRCN). MRCN ensures deadlock freedom by utilizing extended routing and router labeling rules. Furthermore, destination router partitioning and traffic-aware adaptive branching are incorporated to reduce packet routing hops and disperse channel traffic. The effectiveness of MRCN was verified using Noxim, a well-known cycle-accurate NoC simulator, under various topologies and traffic patterns. The simulation revealed that MRCN improved the average latency by 13.98 % and the throughput by 12.16 % under the saturated traffic conditions over the previous multicast routings in customized NoCs.

A New Hybrid Hierarchical Parallel Algorithm to Enhance the Performance of Large-Scale Structural Analysis Based on Heterogeneous Multicore Clusters

Heterogeneous multicore clusters are becoming more popular for high-performance computing due to their great computing power and cost-to-performance effectiveness nowadays. Nevertheless, parallel efficiency degradation is still a problem in large-scale structural analysis based on heterogeneous multicore clusters. To solve it, a hybrid hierarchical parallel algorithm (HHPA) is proposed on the basis of the conventional domain decomposition algorithm (CDDA) and the parallel sparse solver. In this new algorithm, a three-layer parallelization of the computational procedure is introduced to enable the separation of the communication of inter-nodes, heterogeneous-core-groups (HCGs) and inside-heterogeneous-core-groups through mapping computing tasks to various hardware layers. This approach can not only achieve load balancing at different layers efficiently but can also improve the communication rate significantly through hierarchical communication. Additionally, the proposed hybrid parallel approach in this article can reduce the interface equation size and further reduce the solution time, which can make up for the shortcoming of growing communication overheads with the increase of interface equation size when employing CDDA. Moreover, the distributed sparse storage of a large amount of data is introduced to improve memory access. By solving benchmark instances on the Shenwei-Taihuzhiguang supercomputer, the results show that the proposed method can obtain higher speedup and parallel efficiency compared with CDDA and more superior extensibility of parallel partition compared with the two-level parallel computing algorithm (TPCA).

Retracted: Heterogeneous Multi UAV Mission Planning Based on Ant Colony Algorithm Powered BP Neural Network.

[This retracts the article DOI: 10.1155/2021/4369201.].

Prevalence, Antimicrobial Resistance, and Molecular Characterization of Escherichia coli Isolated from Food Contact Surfaces in Seafood Pre-Processing Plants (India)

Background: The survival of pathogens in biofilms poses a threat to food safety. The aim of this study was to determine prevalence, antimicrobial resistance, and molecular characterization of Escherichia coli strains.&#x0D; Methods: Swab samples (n=144) were collected from biofilm formed on food contact surfaces in seafood pre-processing plant in India. E. coli was isolated and identified using uid A gene by Polymerase Chain Reaction (PCR). The risk assessment of the isolates was carried out in terms of their drug resistance and the presence of virulence genes. Antimicrobial susceptibility testing was performed using the Kirby-Bauer disk diffusion method. Phylogenetic grouping was done by quadruplex PCR. Molecular typing of the strains was performed by Enterobacterial Repetitive Intergenic Consensus-PCR (ERIC-PCR). Data were statistically analyzed using SPSS version 22.&#x0D; Results: Enteropathogenic E. coli (EPEC) strains were the most prevalent serotype. Multiplex PCR analysis revealed the presence of shiga toxin genes (stx1, stx2), intimin (eae), and enterohemolysin genes (hlyA). Shiga toxin gene stx2 showed the highest prevalence (83.33%). Among various phylogroups, B1 (45.56%) and B2 (30%) were the most prevalent phylogroups. Resistance to ampicillin (85.56%), piperacillin (84.44%), and cefpodoxime (85.56%) was widespread among the E. coli strains.&#x0D; Conclusion: The presence of genetically heterogeneous multi drug resistant E. coli strains with virulence potential showed a high risk in the seafood industry.

Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores

Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores

Computing exact WCRT for typed DAG tasks on heterogeneous multi-core processors

Heterogeneous multi-core architectures achieve high performance and energy efficiency in real-time domain towards various applications. Most real-time parallel applications on heterogeneous multi-cores can be modeled as a typed directed acyclic graph (DAG) task, where the workload of each vertex is only allowed to execute on a particular type of core. Traditional worst-case response time (WCRT) analysis methods for these applications modeled as DAG are very pessimistic and impractical, i.e., there is a big gap between existing WCRT bounds and the exact WCRT. In this paper, we propose a satisfiability modulo theories-based method to exactly analyze the WCRT of the typed DAG task scheduled upon heterogeneous multi-cores. Experimental results show that our method can significantly improve the precision of the WCRT, and thus, dramatically increase the acceptance rate in the schedulability analysis.

Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contention

Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contention

Energy-Efficient Cache-Aware Scheduling on Heterogeneous Multicore Systems

The adoption of heterogeneous multicore architectures into deadline-constrained embedded systems has various benefits in terms of schedulability and energy-efficiency. Existing energy-efficient algorithms, in this domain, allocate tasks to their energy-favorable core-types while using dynamic voltage and frequency scaling to reduce energy consumption. However, the practicality of such algorithms is limited due to the underlying assumptions made to simplify the analysis. This article paves the way for more practical approaches to minimize the energy consumption on heterogeneous multicores. Specifically, we investigate the nonlinear impacts that core-frequency and cache-partitioning have on task-executions in a heterogeneous multicore environment. In doing so, we propose an algorithm that exploits this relationship to effectively allocate tasks to specific cores and core-types, and determine the number of cache-partitions for each core. Extensive simulations using real-world benchmarks show the proficiency of our approach by achieving an average and maximum energy savings of 14.9 and 20.4 percent, respectively for core-level energy consumption, and 20.2 and 60.4 percent, respectively for system-level energy consumption.

Feasible Coalitions Formation and Tasks Allocation in Heterogeneous Multi Agent System: A Similarity Matching Based Approach

Feasible Coalitions Formation and Tasks Allocation in Heterogeneous Multi Agent System: A Similarity Matching Based Approach

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 32$ </tex-math></inline-formula> -bit tiles and 316 MOPS for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 64$ </tex-math></inline-formula> -bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.

A Survey of Neural Network Hardware Accelerators in Machine Learning

The use of Machine Learning in Artificial Intelligence is the inspiration that shaped technology as it is today. Machine Learning has the power to greatly simplify our lives. Improvement in speech recognition and language understanding help the community interact more naturally with technology. The popularity of machine learning opens up the opportunities for optimizing the design of computing platforms using welldefined hardware accelerators. In the upcoming few years, cameras will be utilised as sensors for several applications. For ease of use and privacy restrictions, the requested image processing should be limited to a local embedded computer platform and with a high accuracy. Furthermore, less energy should be consumed. Dedicated acceleration of Convolutional Neural Networks can achieve these targets with high flexibility to perform multiple vision tasks. However, due to the exponential growth in technology constraints (especially in terms of energy) which could lead to heterogeneous multicores, and increasing number of defects, the strategy of defect-tolerant accelerators for heterogeneous multi-cores may become a main micro-architecture research issue. The up to date accelerators used still face some performance issues such as memory limitations, bandwidth, speed etc. This literature summarizes (in terms of a survey) recent work of accelerators including their advantages and disadvantages to make it easier for developers with neural network interests to further improve what has already been established.

A Meshless Method with Radial Basis Function for Solving Unsaturated Flow in Heterogeneous Porous Media

This paper presents a study for solving unsaturated flow in heterogeneous porous media using the meshless method with the radial basis function (RBF). For modeling the nonlinear hydrological process in unsaturated zone, an exponential model is introduced in the Richards equation such that we may obtain the linearized Richards equation. We adopt the multiquadric function as the RBF in the meshless method for solving the linearized Richards equation. For simulating the unsaturated flow problems in layered heterogeneous soils, the flux and the head must satisfy the continuity condition at the interface. Several examples are carried out for modeling the hydrological process in multi–layered unsaturated soils. The results demonstrate that we only discretize by a set of points without tedious mesh generation and significantly enhance the applicability for solving unsaturated flow problems, especially in heterogeneous multi–layered soils with extreme physical property contrasts.