Heterogeneous Multi-core Architectures Research Articles

Homogeneous and Heterogeneous Multicore Systems

Multicore systems have gained significant importance in the Automotive industry due to data- intensive applications, such as image processing, high- speed process, and GPS application. It enables manufacturers to build smaller chips, simplifying board architecture and routing, reducing power consumption and cost and increasing programmability. Multicore platforms are segregated into two categories namely Homogeneous (symmetric) and Heterogeneous (asymmetric) multicore systems. In Homogeneous systems, all cores are the same, including frequencies, cache sizes and functions. In Heterogeneous systems, different cores operate with different frequencies, cache sizes and functions. In this paper, we are going to discuss various aspects of homogeneous and heterogeneous multicore architectures like number and level of caches, interconnection of the cores, Physical and Temporal isolation, Energy Efficiency, Concurrency, Performance, Reliability and Robustness along with the evaluation of these two architectures for applications based on the above-mentioned aspects.

Adaptive neural acceleration unit based on heterogeneous multicore hardware architecture FPGA and software-defined hardware

ABSTRACT This study is anchored in a heterogeneous multicore hardware architecture, specifically Field Programmable Gate Arrays (FPGAs), and software-defined hardware. It employs dynamic planning for the reconfiguration of a software-defined System-on-Chip (SOC) to expedite neural network processes. The reconfigured software-defined SOC serves as an efficient data processor, facilitating the hybrid development and verification of domain-specific System-on-Chip architectures, adhering to the Advanced Microcontroller Bus Architecture (AMBA) standard. The proposed block data trimming methodology significantly enhances overall hybrid computing efficiency by mitigating throughput limitations inherent in Systolic array hardware. The designed Systolic array Matrix Multiply Unit (MMU) is evaluated for a maximum MMU size of 32 × 32 and 1,024 Multiply Accumulator (MAC) units. Hybrid dynamic circuits are devised for the synthesis of int8, int16, int32, and int64 data types and associated logic circuits to validate the performance of parallel computing. It is anticipated that this proposed system can find utility in the development and deployment of unmanned devices, as well as in the integration of deep learning and multi-sensory fusion involving acoustic, tactile, and force sensory components.

Efficient Large-Scale Virtual Screening Based on Heterogeneous Many-Core Supercomputing System.

With the rapid growth of virtual drug data- bases, the need for efficient molecular docking tools for large-scale screening is also growing. We have developed Vina@QNLM 2.0, a novel molecular docking system that leverages the logical processing units and computational processing arrays of heterogeneous multicore architecture processors. Compared to Vina@QNLM, the new version optimizes the docking speed without sacrificing accuracy. This greatly improves the scoring capability for large molecules (molecular weight > 500). Simultaneously, the new system provides enhanced support for applications such as reverse target finding through an improved parallel strategy. Vina@QNLM 2.0 achieves a speedup 20 times higher than that, using logical processing units only during a single docking process. Additionally, we successfully scaled the reverse target finding a task to 122,401 kernel groups with a robust scalability of 80.01%. In practice, we completed a reverse target-seeking for nine glycan molecules with 10,094 proteins within 1 hour.

Implementation of Real-Time Space Target Detection and Tracking Algorithm for Space-Based Surveillance

Space-based target surveillance is important for aerospace safety. However, with the increasing complexity of the space environment, the stellar target and strong noise interference pose difficulties for space target detection. Simultaneously, it is hard to balance real-time processing with computational performance for the onboard processing platform owing to resource limitations. The heterogeneous multi-core architecture has corresponding processing capabilities, providing a hardware implementation platform with real-time and computational performance for space-based applications. This paper first developed a multi-stage joint detection and tracking model (MJDTM) for space targets in optical image sequences. This model combined an improved local contrast method and the Kalman filter to detect and track the potential targets and use differences in movement status to suppress the stellar targets. Then, a heterogeneous multi-core processing system based on a field-programmable gate array (FPGA) and digital signal processor (DSP) was established as the space-based image processing system. Finally, MJDTM was optimized and implemented on the above image processing system. The experiments conducted with simulated and actual image sequences examine the accuracy and efficiency of the MJDTM, which has a 95% detection probability while the false alarm rate is 10−4. According to the experimental results, the algorithm hardware implementation can detect targets in an image with 1024 × 1024 pixels in just 22.064 ms, which satisfies the real-time requirements of space-based surveillance.

Federated Scheduling Optimization Scheme for Typed Tasks With Power Constraints in Heterogeneous Multicore Processor Architectures

Federated Scheduling Optimization Scheme for Typed Tasks With Power Constraints in Heterogeneous Multicore Processor Architectures

Fuzzy Active Learning to Detect OpenCL Kernel Heterogeneous Machines in Cyber Physical Systems

Cyber-physical systems (CPS) consist of a variety of multicore architectures, including central processing units (CPU) and graphical processing units (GPU). In general, programmers assign sequential programs to the CPU while parallel applications are assigned to the GPU. This article provides a method for mapping an OpenCL application to a heterogeneous multicore architecture using active fuzzy learning to determine the adequacy and processing capabilities of the application. During learning, subsamples are created by developing a machine learning-based device suitability classifier that predicts which processors would have excessive computational compatibility for running OpenCL programs. In addition, this study integrates an active learning model based on entropy with a fuzzification model to find nonoverlapping patterns. To minimize rule generation, the fuzzification-based weighted probabilistic technique is presented. The defuzzification process is optimized by using uncertainty values in conjunction with classification probability. In addition, 20 different features are proposed for extraction using the newly developed LLVM-based static analyzer. The correlation analysis approach is used to determine the optimal subset of features. The synthetic minority oversampling approach with and without feature selection is used to differentiate the class imbalance problem. Instead of manually modifying the machine learning classifier, a tree-based pipeline construction approach is used to determine the optimal classifier and associated hyperparameters. Experiments are then conducted on a set of benchmarks to verify the performance of the designed model. The results show that by increasing the number of training examples and including an entropy uncertainty measure, the proposed model is able to support and improve decision boundaries. We achieved a high F-measure of 0.77 and a ROC of 0.92 by optimizing and reducing the feature subsets.

OpenVVC Decoder Parameterized and Interfaced Synchronous Dataflow (PiSDF) Model: Tile Based Parallelism.

The emergence of the new video coding standard, Versatile Video Coding (VVC), has resulted in a 40-50% coding gain over its predecessor HEVC for the same visual quality. However, this is accompanied by a sharp increase in computational complexity. The emergence of the VVC standard and the increase in video resolution have exceeded the capacity of single-core architectures. This fact has led researchers to use multicore architectures for the implementation of video standards and to use the parallelism of these architectures for real-time applications. With the strong growth in both areas, video coding and multicore architecture, there is a great need for a design methodology that facilitates the exploration of heterogeneous multicore architectures, which automatically generates optimized code for these architectures in order to reduce time to market. In this context, this paper aims to use the methodology based on data flow modeling associated with the PREESM software. This paper shows how the software has been used to model a complete standard VVC video decoder using Parameterized and Interfaced Synchronous Dataflow (PiSDF) model. The proposed model takes advantage of the parallelism strategies of the OpenVVC decoder and in particular the tile-based parallelism. Experimental results show that the speed of the VVC decoder in PiSDF is slightly higher than the OpenVVC decoder handwritten in C/C++ languages, by up to 11% speedup on a 24-core processor. Thus, the proposed decoder outperforms the state-of-the-art dataflow decoders based on the RVC-CAL model.

Computing exact WCRT for typed DAG tasks on heterogeneous multi-core processors

Heterogeneous multi-core architectures achieve high performance and energy efficiency in real-time domain towards various applications. Most real-time parallel applications on heterogeneous multi-cores can be modeled as a typed directed acyclic graph (DAG) task, where the workload of each vertex is only allowed to execute on a particular type of core. Traditional worst-case response time (WCRT) analysis methods for these applications modeled as DAG are very pessimistic and impractical, i.e., there is a big gap between existing WCRT bounds and the exact WCRT. In this paper, we propose a satisfiability modulo theories-based method to exactly analyze the WCRT of the typed DAG task scheduled upon heterogeneous multi-cores. Experimental results show that our method can significantly improve the precision of the WCRT, and thus, dramatically increase the acceptance rate in the schedulability analysis.

Energy-Efficient Cache-Aware Scheduling on Heterogeneous Multicore Systems

The adoption of heterogeneous multicore architectures into deadline-constrained embedded systems has various benefits in terms of schedulability and energy-efficiency. Existing energy-efficient algorithms, in this domain, allocate tasks to their energy-favorable core-types while using dynamic voltage and frequency scaling to reduce energy consumption. However, the practicality of such algorithms is limited due to the underlying assumptions made to simplify the analysis. This article paves the way for more practical approaches to minimize the energy consumption on heterogeneous multicores. Specifically, we investigate the nonlinear impacts that core-frequency and cache-partitioning have on task-executions in a heterogeneous multicore environment. In doing so, we propose an algorithm that exploits this relationship to effectively allocate tasks to specific cores and core-types, and determine the number of cache-partitions for each core. Extensive simulations using real-world benchmarks show the proficiency of our approach by achieving an average and maximum energy savings of 14.9 and 20.4 percent, respectively for core-level energy consumption, and 20.2 and 60.4 percent, respectively for system-level energy consumption.

An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning

With the growing interest of edge computing in the Internet of Things (IoT), Deep Neural Network (DNN) hardware processors/accelerators face challenges of low energy consumption, low latency, and data privacy issues. This paper proposes an energy-efficient processor design based on Deep Belief Network (DBN), which is one of the most suitable DNN models for on-chip learning. In this study, a thorough algorithm-architecture-circuit design optimization method is used for efficient design. The characteristics of data reuse and data sparsity in the DBN learning algorithm inspires this study to propose a heterogeneous multi-core architecture with local learning. In addition, novel circuits of transposable weight memory and sparse address generator are proposed to reduce weight memory access and exploit neuron state sparsity, respectively, for maximizing the energy efficiency. The DBN processor is implemented and thoroughly evaluated on Xilinx Zynq FPGA. Implementation results confirm that the proposed DBN processor has excellent energy efficiency of 45.0 pJ per neuron-weight update, which has been improved by 74% against the conventional design.

Redesigning Vina@QNLM for Ultra-Large-Scale Molecular Docking and Screening on a Sunway Supercomputer.

Ultra-large-scale molecular docking can improve the accuracy of lead compounds in drug discovery. In this study, we developed a molecular docking piece of software, Vina@QNLM, which can use more than 4,80,000 parallel processes to search for potential lead compounds from hundreds of millions of compounds. We proposed a task scheduling mechanism for large-scale parallelism based on Vinardo and Sunway supercomputer architecture. Then, we readopted the core docking algorithm to incorporate the full advantage of the heterogeneous multicore processor architecture in intensive computing. We successfully expanded it to 10, 465, 065 cores (1,61,001 management process elements and 0, 465, 065 computing process elements), with a strong scalability of 55.92%. To the best of our knowledge, this is the first time that 10 million cores are used for molecular docking on Sunway. The introduction of the heterogeneous multicore processor architecture achieved the best speedup, which is 11x more than that of the management process element of Sunway. The performance of Vina@QNLM was comprehensively evaluated using the CASF-2013 and CASF-2016 protein–ligand benchmarks, and the screening power was the highest out of the 27 pieces of software tested in the CASF-2013 benchmark. In some existing applications, we used Vina@QNLM to dock more than 10 million molecules to nine rigid proteins related to SARS-CoV-2 within 8.5 h on 10 million cores. We also developed a platform for the general public to use the software.

BiCoSS: Toward Large-Scale Cognition Brain With Multigranular Neuromorphic Architecture.

The further exploration of the neural mechanisms underlying the biological activities of the human brain depends on the development of large-scale spiking neural networks (SNNs) with different categories at different levels, as well as the corresponding computing platforms. Neuromorphic engineering provides approaches to high-performance biologically plausible computational paradigms inspired by neural systems. In this article, we present a biological-inspired cognitive supercomputing system (BiCoSS) that integrates multiple granules (GRs) of SNNs to realize a hybrid compatible neuromorphic platform. A scalable hierarchical heterogeneous multicore architecture is presented, and a synergistic routing scheme for hybrid neural information is proposed. The BiCoSS system can accommodate different levels of GRs and biological plausibility of SNN models in an efficient and scalable manner. Over four million neurons can be realized on BiCoSS with a power efficiency of 2.8k larger than the GPU platform, and the average latency of BiCoSS is 3.62 and 2.49 times higher than conventional architectures of digital neuromorphic systems. For the verification, BiCoSS is used to replicate various biological cognitive activities, including motor learning, action selection, context-dependent learning, and movement disorders. Comprehensively considering the programmability, biological plausibility, learning capability, computational power, and scalability, BiCoSS is shown to outperform the alternative state-of-the-art works for large-scale SNN, while its real-time computational capability enables a wide range of potential applications.

Reconfigurable architecture for heterogeneous multi-core and many-core architecture with IoT assistance

Reconfigurable architecture for heterogeneous multi-core and many-core architecture with IoT assistance

Reconfigurable architecture for heterogeneous multi-core and many-core architecture with IoT assistance

Reconfigurable architecture for heterogeneous multi-core and many-core architecture with IoT assistance

Performance optimization of non-equilibrium ionization simulations from MapReduce and GPU acceleration

We propose a two-stage optimization strategy to accelerate non-equilibrium ionization (NEI) calculation that is crucial to various high energy astrophysical phenomena, by using methods of MapReduce modeling and GPU acceleration. First, we construct a parallel pipeline based on the MapReduce model that processes massive particles trajectories on a separate mesh decoupled from that has been used by other equations in the multiphysics simulations. Second, we accelerate the calculation of massive NEI equations by taking full advantage of heterogeneous multicore architecture of GPUs. The approach has been prototyped and tested in simulations using FLASH code and AtomDB atomic database. Our results show that the method can improve the end-to-end performance by 3-fold with less computing resources and reduce the overhead significantly. For standalone tests, the GPU-accelerated NEI solver can achieve a maximum 212-fold speedup compared to the CPU-based solver. With the capability to support nonintrusive simulation-time data analysis, our approach can be also applied to other multiphysics processes such as reactive flow simulations.

Bi-Directional Timing-Power Optimisation on Heterogeneous Multi-Core Architectures

Optimisation of timing performance and power consumption on heterogeneous multi-core architectures is gaining increasing attention. Systems and devices may have varying demands on timing and power, which motivates more flexible optimisation. Along this line, we consider a heterogeneous computing architecture with multiple cores, where each core runs a mixed stream of general and dedicated tasks with a certain scheduling strategy. Employing the queuing model, we first propose a load balancing algorithm, which minimises the average response time of the general tasks whilst guaranteeing the timing requirements of the dedicated tasks. Built upon the above, we propose a bi-directional optimisation algorithm that is able to improve the timing performance under the constraint of power consumption, and reduces the power consumption for the given timing requirement. Extensive numerical experiments illustrate the significance of the proposed algorithms. Implementation on a real platform validates the consistency between the theoretical analysis and the practical results.

A load balance multi-scheduling model for OpenCL kernel tasks in an integrated cluster

Nowadays, embedded systems are comprised of heterogeneous multi-core architectures, i.e., CPUs and GPUs. If the application is mapped to an appropriate processing core, then these architectures provide many performance benefits to applications. Typically, programmers map sequential applications to CPU and parallel applications to GPU. The task mapping becomes challenging because of the usage of evolving and complex CPU- and GPU-based architectures. This paper presents an approach to map the OpenCL application to heterogeneous multi-core architecture by determining the application suitability and processing capability. The classification is achieved by developing a machine learning-based device suitability classifier that predicts which processor has the highest computational compatibility to run OpenCL applications. In this paper, 20 distinct features are proposed that are extracted by using the developed LLVM-based static analyzer. In order to select the best subset of features, feature selection is performed by using both correlation analysis and the feature importance method. For the class imbalance problem, we use and compare synthetic minority over-sampling method with and without feature selection. Instead of hand-tuning the machine learning classifier, we use the tree-based pipeline optimization method to select the best classifier and its hyper-parameter. We then compare the optimized selected method with traditional algorithms, i.e., random forest, decision tree, Naïve Bayes and KNN. We apply our novel approach on extensively used OpenCL benchmarks, i.e., AMD and Polybench. The dataset contains 653 training and 277 testing applications. We test the classification results using four performance metrics, i.e., F-measure, precision, recall and R^2. The optimized and reduced feature subset model achieved a high F-measure of 0.91 and R^2 of 0.76. The proposed framework automatically distributes the workload based on the application requirement and processor compatibility.

Modeling and simulation of power consumption and execution times for real-time tasks on embedded heterogeneous architectures

In this work, we introduce a power-consumption model for heterogeneous multicore architectures that captures the variability of energy consumption based on processing workload type, in addition to the classical variables considered in the literature, like type and frequency of the CPU. We motivate the approach presenting experimental results gathered on a Odroid-XU3 board equipped with an Arm big.LITTLE CPU, showing that power consumption has a non-negligible dependency on the workload type. We also present a model to define the execution time of the tasks, which depends on both the workload, and the CPU frequency and architecture. We present our modifications to the open-source RTSIM real-time scheduling simulator to extend its CPU power consumption and execution time duration models, integrating results taken from the real platform. The presented work constitutes a useful base for future research in power-aware real-time scheduling on heterogeneous platforms.

Energy-Aware Core Switching for Mobile Devices with a Heterogeneous Multicore Processor

Mobile devices should be designed to meet two contradictory goals: providing the performance desired by users while minimizing the energy consumption to meet the users' expectation of the battery run-time. The heterogeneous multicore architecture has been introduced to mobile world for higher energy-efficiency and performance. It is possible, however, only when the operating system assigns the appropriate core for an application to take full advantage of the heterogeneity. This article addresses the problem of the core selection for mobile devices with a heterogeneous multicore processor. It is shown that core switching for less energy consumption must consider both core frequency and utilization at the same time.

Research on Identity Mechanism of Large-scale Drug Virtual Screening in Heterogeneous Multicore Environment and SMP Environment

This paper studies the mechanism of ultra-large-scale drug virtual screening in the heterogeneous multicore environment and SMP (Symmetric Multi-Processor) environment. Given the differences caused by different CPUs, we solved the incompatibility of the open-source molecular docking software Autodock Vina on two supercomputer systems in different environments and realized the automatic and intelligent large-scale virtual screening process for small-molecule ligands. At the same time, we propose a processing method of large-scale virtual screening using Autodock Vina in two environments, which makes full use of the dominant computing power of supercomputers to improve the efficiency of large-scale molecular docking and reduce the load of different supercomputer systems facing large-scale molecular docking tasks. Finally, we conduct a virtual screening experiment on the X86 platform supercomputer and the Sunway TaihuLight Supercomputer based on the heterogeneous multicore architecture CPU—SW26010. The experimental results show that our large-scale drug virtual screening method for different CPU environments is effective.