Heterogeneous Multicore Platforms Research Articles

Energy-efficient triple modular redundancy scheduling on heterogeneous multi-core real-time systems

Triple modular redundancy (TMR) fault tolerance mechanism can provide almost perfect fault-masking, which has the great potential to enhance the reliability of real-time systems. However, multiple copies of a task are executed concurrently, which will lead to a sharp increase in system energy consumption. In this work, the problem of parallel applications using TMR on heterogeneous multi-core platforms to minimize energy consumption is studied. First, the heterogeneous earliest finish time algorithm is improved, and then according to the given application's deadline constraints and reliability requirements, an algorithm to extend the execution time of the copies is designed. Secondly, based on the properties of TMR, an algorithm for minimizing the execution overhead of the third copy (MEOTC) is designed. Finally, considering the actual situation of task execution, an online energy management (OEM) method is proposed. The proposed algorithms were compared with the state-of-the-art AFTSA algorithm, and the results show significant differences in energy consumption. Specifically, for light fault detection, the energy consumption of the MEOTC and OEM algorithms was found to be 80% and 72% respectively, compared with AFTSA. For heavy fault detection, the energy consumption of MEOTC and OEM was measured at 61% and 55% respectively, compared with AFTSA.

Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded Systems

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS

Heterogeneous multi-core platforms, such as ARM big.LITTLE are widely used to execute embedded applications under multiple and contradictory constraints, such as energy consumption and real-time execution. To fulfill these constraints and optimize system performance, application tasks should be efficiently mapped on multi-core platforms. Embedded applications are usually tolerant to approximated results but acceptable Quality-of-Service (QoS). Modeling embedded applications by using the elastic task model, namely, Imprecise Computation (IC) task model, can balance system QoS, energy consumption, and real-time performance during task deployment. However, state-of-the-art approaches seldom consider the problem of IC task deployment on heterogeneous multi-core platforms. They typically neglect task migration, which can improve the solutions due to its flexibility during the task deployment process. This paper proposes a novel QoS-aware task deployment method to maximize system QoS under energy and real-time constraints, where frequency assignment, task allocation, scheduling, and migration are optimized simultaneously. The task deployment problem is formulated as mixed-integer non-linear programming. Then, it is linearized to mixed-integer linear programming to find the optimal solution. Furthermore, based on problem structure and problem decomposition, we propose a novel heuristic with low computational complexity. The sub-problems regarding frequency assignment, task allocation, scheduling, and adjustment are considered and solved in sequence. Finally, the simulation results show that the proposed task deployment method improves the system QoS by 31.2% on average (up to 112.8%) compared to the state-of-the-art methods and the designed heuristic achieves about 53.9% (on average) performance of the optimal solution with a negligible computing time.

Approx-RM: Reducing Energy on Heterogeneous Multicore processors under Accuracy and Timing Constraints

Reducing energy consumption while providing performance and quality guarantees is crucial for computing systems ranging from battery-powered embedded systems to data centers. This paper considers approximate iterative applications executing on heterogeneous multi-core platforms under user-specified performance and quality targets. We note that allowing a slight yet bounded relaxation in solution quality can considerably reduce the required iteration count and thereby can save significant amounts of energy. To this end, this paper proposes Approx-RM , a resource management scheme that reduces energy expenditure while guaranteeing a specified performance as well as accuracy target. Approx-RM predicts the number of iterations required to meet the relaxed accuracy target at run-time. The time saved generates execution-time slack, which allows Approx-RM to allocate fewer resources on a heterogeneous multi-core platform in terms of DVFS, core type, and core count to save energy while meeting the performance target. Approx-RM contributes with lightweight methods for predicting the iteration count needed to meet the accuracy target and the resources needed to meet the performance target. Approx-RM uses the aforementioned predictions to allocate just enough resources to comply with quality of service constraints to save energy. Our evaluation shows energy savings of 31.6%, on average, compared to Race-to-idle when the accuracy is only relaxed by 1%. Approx-RM incurs timing and energy overheads of less than 0.1%.

Parallel swarm-based algorithms for scheduling independent tasks

Task scheduling is crucial for achieving high performance in parallel computing. Since task scheduling is NP-hard, the efficient assignment of tasks to compute resources remains an issue. Across the literature, several algorithms have been proposed to solve different scheduling problems. One group of promising approaches in this field is formed by swarm-based algorithms which have a potential to benefit from a parallel execution. Common swarm-based algorithms are Ant Colony Optimization (ACO) and Particle Swarm Optimization (PSO). In this article, we propose two new scheduling methods based on parallel ACO, PSO and, Hill Climbing, respectively. These algorithms are used to solve the problem of scheduling independent tasks onto heterogeneous multicore platforms. The results of performance measuements demonstrate the improvements on the makespan and the scheduling time achieved by the parallel variants.

Type-Aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms

To utilize the performance benefits of heterogeneous multicore platforms in real-time systems, we need task models that expose the parallelism and heterogeneity of the workload, such as typed DAG tasks, as well as scheduling algorithms that effectively exploit this information. In this paper, we introduce <i>type-aware federated scheduling</i> algorithms for sporadic typed DAG tasks with implicit deadlines running on a heterogeneous multicore platform with two different types of cores. In type-aware federated scheduling, a task can be executed in one of the three strategies: <i>Exclusive Allocation</i>, <i>Semi-Exclusive Allocation</i>, and <i>Sequential and Share</i>. In <i>Exclusive Allocation</i>, clusters of cores of both core types are exclusively allocated to tasks, while cores of only one type are exclusively allocated to tasks in <i>Semi-Exclusive Allocation</i>. The workload of the other type from tasks in <i>Semi-Exclusive Allocation</i> and the workload from tasks in <i>Sequential and Share</i> share the cores that are not exclusively allocated to any task. We prove that our type-aware federated scheduling algorithm has a capacity augmentation bound of 7.25. We also show that no constant capacity augmentation bound can be obtained without <i>Semi-Exclusive Allocation</i>. Compared to the state of the art, the type-aware federated scheduling algorithm achieves better schedulability, especially for task sets with skewed workload.

Analyzing Arm's MPAM From the Perspective of Time Predictability

With heterogeneous multi-core platforms being crucial to execute the highly demanding workloads of modern applications, memory-access predictability remains a key issue for the system's safety. Many solutions have been proposed over the years, but none has been applied on a large scale. Nowadays, we are in front of an unprecedented opportunity to have an impact on commercial platforms: the Memory System Resource Partitioning and Monitoring (MPAM) specification by Arm, which describes different memory-access regulation mechanisms, presenting a valuable industrial attempt to address this issue. However, several points of the specification are described at a high level only, leaving plenty of room for interpretation to hardware manufacturers. This paper takes a close look at the memory-access regulation mechanisms in the MPAM specification and provides some detailed instantiations of such mechanisms. A fine-grained memory contention analysis is presented for each of them to finally enable a comparison of their worst-case performance.

A new direct acyclic graph task scheduling method for heterogeneous Multi-Core processors

At present, the traditional methods of calculating the worst response time upper bounds for direct acyclic graph (DAG) task scheduling on heterogeneous multi-core platforms suffer from problems such as nonself-sustainability, too many blocking nodes, and excessive estimation of the overhead time required for task scheduling, all of which cause response time upper bound estimates to be far too pessimistic. We propose to reconstruct the DAG graph by adding execution edges in order to eliminate blocking nodes. The specific method is to first use triples to represent each node of the DAG task graph, then to select blocking nodes according to the priority rules with which we add execution edges graph to reconstruct it, and finally to remove the blocking nodes again and repeat the process until all blocking nodes have been eliminated. Our experiments show that the worst response time upper bound from this method can achieve a 20% improvement in accuracy compared to the traditional methods for calculating the worst response time upper bound.

Implementation of a real‐time stereo vision algorithm on a cost‐effective heterogeneous multicore platform

SummaryStereo vision is a major computer vision technique commonly used for robotics applications. Existing software implementations of this technique on general‐purpose processors offer low time‐to‐market compared to other platforms. However, such implementations can hardly achieve real‐time and their cost is usually relatively high. These issues can be solved by embedded multicore platforms. In this article, we present a low‐cost, improved software implementation of a stereo matching algorithm in the correlation stage that combines a sparse rank transform with a combination of sum of absolute differences 1‐D and 2‐D box filtering algorithms. A circular buffer scheme is used to optimize memory usage during the rank computation stage. The system runs on a heterogeneous multicore platform (ODROID XU4). Through the extensive use of single instruction multiple data Neon intrinsics, the system can process images with a size of pixels and a disparity range of 20 pixels at a rate of 111 frames per second. The proposed system can be used in mobile robot platforms that require low power consumption while delivering real‐time performance.

RT-SEAT: A hybrid approach based real-time scheduler for energy and temperature efficient heterogeneous multicore platforms

The demand for heterogeneous multicore platforms is growing at a rapid pace in modern gadgets. Such platforms help cater to various types of applications and thus provide high resource utilization. As each task has a different execution time on different types of cores, it is very challenging to schedule tasks on such platforms. With the advancement in technology, it has become imperative to manage energy consumption and temperatures of cores in multicore platforms. Hence, in this work, we propose RT-SEAT, a hybrid real-time scheduler for energy and temperature-efficient heterogeneous multicore systems. Through extensive experimental analysis, we have found that RT-SEAT is able to schedule more tasks (up to 46.75%), save more energy (up to 6.89%), and reduce the average temperature of the cores by 20.45%, when the system workload varies from 50% to 100%, with respect to the state-of-the-art.

Design and Implementation of a Dynamic Task Mapping Algorithm Based on Hotspot Statistics

In a coarse-grained heterogeneous multi-core system, the task map is responsible for allocating the cores for task execution. The existing user static mapping method has low programming friendliness. As the scale and density of system tasks increase, so does the complexity of manual programming by users, resulting in programming inefficiencies. Aiming at this problem, based on the existing heterogeneous multi-core platform, this paper studies a dynamic task mapping method with hotspot statistics, and uses the preprocessing of the mapping to reduce the time spent on the actual mapping. The hardware mapper is designed and implemented in Verilog, and the verification platform is built in the HDL environment. The experimental results show that the new mapping algorithm significantly improves the performance of the system, with an average of 32.50% and a maximum of 47.16%.

Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems

Recent trends in real-time applications have raised the demand for high-throughput embedded platforms with integrated CPU-GPU based Systems-On-Chip (SoCs). The enhanced performance of such SoCs, however, comes at the cost of increased power consumption, resulting in significant heat dissipation and high on-chip temperatures. The prolonged occurrences of high on-chip temperature can cause accelerated in-circuit ageing, which severely degrades the long-term performance and reliability of the chip. Violation of thermal constraints leads to on-board dynamic thermal management kicking-in, which may result in timing unpredictability for real-time tasks due to transient performance degradation. Recent work in adaptive software design have explored this issue from a control theoretic stand-point, striving for smooth thermal envelopes by tuning the core frequency. Existing techniques do not handle thermal violations for periodic real-time task sets in the presence of dynamic events like change of task periodicity, more so in the context of heterogeneous SoCs with integrated CPU-GPUs. This work presents an OpenCL runtime extension for thermal-aware scheduling of periodic, real-time tasks on heterogeneous multi-core platforms. Our framework mitigates dynamic thermal violations by adaptively tuning task mapping parameters, with the eventual control objective of satisfying both platform-level thermal constraints and task-level deadline constraints. We consider multiple platform-level control actions like task migration, frequency tuning and idle slot insertion as the task mapping parameters. To the best of our knowledge, this is the first work that considers such a variety of task mapping control actions in the context of heterogeneous embedded platforms. We evaluate the proposed framework on an Odroid-XU4 board using OpenCL benchmarks and demonstrate its effectiveness in reducing thermal violations.

Concurrent Application Bias Scheduling for Energy Efficiency of Heterogeneous Multi-Core Platforms

Minimizing energy consumption of concurrent applications on heterogeneous multi-core platforms is challenging given the diversity in energy-performance profiles of both the applications and hardware. Adaptive learning techniques made the exhaustive Pareto-optimal space exploration practically feasible to identify an energy efficient configuration. Existing approaches consider a single application's characteristic for optimizing energy consumption. However, an optimal configuration for a given application in isolation may not be optimal when other applications are run concurrently. Approaches that consider concurrent application scenarios overlook the weight of total energy consumption per application, restricting them from prioritizing among applications. We address this limitation by considering the mutual effect of concurrent applications on system wide energy consumption to adapt resource configuration at run-time. We characterize each application's power-performance profile as a weighted bias through off-line profiling. We infer this model combined with an on-line predictive strategy to make resource allocation decisions for minimizing energy consumption while honoring performance requirements. The proposed strategy is implemented as a user-space process and evaluated on a heterogeneous hardware platform of Odroid XU3 over the Rodinia benchmark suite. Experimental results show up to 61 percent of energy saving compared to the standard baseline of Linux governors and up to 27 percent of energy gain compared to state-of-the-art adaptive learning-based resource management techniques.

SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorE Real-time Systems

Abstract Over the years, the nature of processing platforms is witnessing a significant shift in most of the battery supported real-time systems, which now support a combination of specialized multicores to meet the demands of modern applications. Devising energy-efficient schedulers has become a critical issue for such kinds of devices. Hence, this research presents a low-overhead heuristic strategy named SEAMERS, for DVFS based energy-aware scheduling for a set of real-time periodic tasks on a heterogeneous multicore platform. The presented strategy operates in four phases, namely Deadline Partitioning, Core Clustering, Task Allocation and Energy-Aware Scheduling. Our experimental analysis shows that the presented strategy improves upon the state-of-the-art in terms of energy savings (16% to 47% on average) and enables significant improvement in resource utilization.

Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform

In modern multi-core Mixed-Criticality (MC) systems, a rise in peak power consumption due to parallel execution of tasks with maximum frequency, specially in the overload situation, may lead to thermal issues, which may affect the reliability and timeliness of MC systems. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power and thermal management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and per-cluster Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our approach examines multiple tasks ahead to determine the most appropriate one for slack assignment, that has the most impact on the system peak power and temperature. However, changing the frequency and selecting a proper task for slack assignment and a proper core for task re-mapping at runtime can be time-consuming and may cause deadline violation which is not admissible for high-criticality tasks. Therefore, we analyze and then optimize our run-time scheduler and evaluate it for various platforms. The proposed approach is experimentally validated on the ODROID-XU3 (DVFS-enabled heterogeneous multi-core platform) with various embedded real-time benchmarks. Results show that our heuristic achieves up to 5.25% reduction in system peak power and 20.33\% reduction in maximum temperature compared to an existing method while meeting deadline constraints in different criticality modes.

A novel gateway-based solution for remote elderly monitoring.

Internet of Things (IoT) technologies have been applied to various fields such as manufacturing, automobile industry and healthcare. IoT-based healthcare has a significant impact on real-time remote monitoring of patients' health and consequently improving treatments and reducing healthcare costs. In fact, IoT has made healthcare more reliable, efficient, and accessible. Two major drawbacks which IoT suffers from can be expressed as: first, thelimited battery capacityof thesensorsis quickly depleted due to the continuous stream of data; second, the dependence of the system on the cloud for computations and processing causes latency in data transmission which is not accepted in real-time monitoring applications. This research is conducted to develop a real-time, secure, and energy-efficient platform which provides a solution for reducing computation load on the cloud and diminishing data transmission delay. In the proposed platform, the sensors utilize a state-of-the-art power saving technique known as Compressive Sensing (CS). CS allows sensors to retrieve the sensed data using fewer measurements by sending a compressed signal. In this framework, the signal reconstruction and processing are computed locally on a Heterogeneous Multicore Platform (HMP) device to decrease the dependency on the cloud. In addition, a framework has been implemented to control the system, set different parameters, display the data as well as send live notifications to medical experts through the cloud in order to alert them of any eventual hazardous event or abnormality and allow quick interventions. Finally, a case study of the system is presented demonstrating the acquisition and monitoring of the data for a given subject in real-time. The obtained results reveal that the proposed solution reduces 15.4% of energy consumption in sensors, that makes this prototype a good candidate for IoT employment in healthcare.

Efficient Open Source Software Radio on Heterogeneous Multicore Embedded Platforms

Software radio is a common technique in modern communications equipment, and it is frequently implemented using heterogeneous multicore processors because of its high computational requirements. Programming such systems is still a challenging task and developers rely often on standard parallel APIs and frameworks such as OpenMP and OpenCL. These tools, however, present some limitations when more than one algorithm has to be accelerated. The typical workload of a software radio usually includes several compute-intensive algorithms so it might be still better served by more specific tools, especially on embedded platforms. In this article, a development methodology for implementing software radio applications in heterogeneous multicore embedded platforms is proposed. The methodology is based on GNU radio, a free and open source software toolkit. To validate the methodology, a DVB–T receiver has been ported to an embedded heterogeneous multicore platform as a proof-of-concept. The results show that two different compute-intensive algorithms, Viterbi decoder, and FFT, can be simultaneously accelerated, improving the DVB–T receiver performance by 63%.

The search‐based scheduling algorithm HP* for parallel tasks on heterogeneous platforms

SummaryScheduling is a widely used method in parallel computing, which assigns tasks to compute resources of a parallel environments. In this article, we consider independent parallel tasks to be scheduled onto a heterogeneous execution platform consisting of a set of multicores of different architecture. Each parallel task has an internal potential parallelism which allows a parallel execution on any multicore processors. However, the execution time may differ due a different computation speed of different multicores. In this article, we propose a new search‐based scheduling algorithm Heterogeneous Parallel task scheduling based on A* (called HP*) to solve the problem of scheduling independent parallel tasks onto heterogeneous multicore platforms. Specifically, we propose a heuristic cost function needed for an informed search. Also, three pruning techniques are proposed, which are shown to significantly reduce the search space of HP*. Performance measurements on a heterogeneous platform are performed and the results of HP* are compared to scheduling results of other popular scheduling methods. The performance results with benchmark tasks from the SPLASH‐3 benchmark suite demonstrate the good scheduling results and the improvements achieved by HP*.

A Real-time Image Recognition System Based on Improved Jacintonet Convolutional Neural Network

With the emergence and development of new automation industries such as unattended supermarkets and smart picking orchards, the demand for real-time systems based on embedded platforms is increasing day by day. Heterogeneous multi-core processors are widely used in modern integrated circuit design due to their advantages of low power consumption and high parallelism. More and more real-time systems are implemented on heterogeneous multi-core platforms. Based on the heterogeneous multi-core embedded system, the network parameters and architecture of jacintonet model are improved, and a real-time system for fruit image recognition is realized by using the improved network. A small sample data set is used to train the modified network and the trained network is imported into the system for testing. The result shows that the improved jacintonet network can run well on heterogeneous multi-core system and has the same recognition performance as the original network.

Reliable and Secure Design-Space-Exploration for Cyber-Physical Systems

Given the widespread deployment of cyber-physical systems and their safety-critical nature, reliability and security guarantees offered by such systems are of paramount importance. While the security of such systems against sensor attacks have garnered significant attention from researchers in recent times, improving the reliability of a control software implementation against transient environmental disturbances need to be investigated further. Scalable formal methods for verification of actual control performance guarantee offered by software implementations of control laws in the face of sensory faults have been explored in recent work [20]. However, the formal verification of the improvement of system reliability by incorporating sensor fault mitigation techniques like Kalman filtering [29] and sensor fusion [18, 52] remains to be explored. Moreover, system designers face complex tradeoff choices for deciding upon the usage of fault and attack mitigation techniques and scheduling them on available system resources as they incur extra computation load. In the present work, our contributions are threefold. We formally analyze the actual performance guarantee of control software implementations enabled with additional fault mitigation techniques. We consider task-level models of such implementations enabled with security and fault tolerance primitives and construct a timed automata-based model which checks for schedulability on heterogeneous multi-core platforms. We leverage these methodologies in the context of a novel Design-Space-Exploration (DSE) framework that considers target reliability and security guarantees for a control system and computes schedulable design options while considering well-known platform-level security improvement and fault mitigation techniques. We validate our contributions over several case studies from the automotive domain.