Heterogeneous Adder Research Articles

HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications

Media processing applications can tolerate error up to a certain limit due to the perceptual limitations of the human eye. Since adders are ubiquitous in power-hungry media processing applications, they can be approximated without much compromise in quality. An adder with better error characteristics without significant compromise in area and power is required to meet the future demands of ever-increasing computational needs. In order to achieve the same, a novel segmentation technique has been proposed. By varying the number of bits in each segment, three different designs are proposed, each with its advantage. Each proposed adder is segmented into three portions, namely Most Significant Portion (MSP), Intermediate Significant Portion (ISP) and Least Significant Portion (LSP). The sub-adder’s sum in each portion is computed concurrently to reduce the critical path delay. The proposed heterogeneous adder (HEAD) designs achieve better accuracy than the state-of-the-art designs. Synthesis results show that HEAD consumes less area up to 41.8% and consumes less power ranging from 0.8% to 51%, than existing adders. Exhaustive simulations are carried out on benchmarking image sharpening application to prove that the proposed adders obtain a better quality-effort tradeoff than the existing designs.

Heterogeneous Adder Based FIR Filter Design And Simulation

The finite impulse response (FIR) is one of the important filters in digital signal processing (DSP) as it responds for a finite duration and settles to zero on the finite time. Digital FIR filters are programmable in nature and its behavior can be understood with the help of the program and can be easily programmed for the memory of a processor. The digital filters can be replaced without change of the hardware or the external circuitry. The 7 tap FIR filter needs 16 numbers of multipliers and 9 adders which are used in parallel form. The paper focused on the chip design and implementation of the FIR filter with a decimal adder and heterogeneous adder is done using VHDL programming in Xilinx 14.2 ISE software and the same is synthesized on SPARTAN - 3E FPGA to verify the results. Moreover, the functional simulation is done in Modelsim 10.0 software. Hardware utilization parameters, combinational path delay, memory utilization parameters are directly extracted from the Xilinx software for FIR filter architecture based on decimal adder and heterogeneous adders. The comparative analysis of the FIR filter is done with heterogeneous adder architecture lead an area and delay efficient design for DSP applications

Simulation and Synthesis of Heterogeneous Adder Using VIVADO

Simulation and Synthesis of Heterogeneous Adder Using VIVADO

ENGLISH

Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer.

VLSI Implementation of Heterogeneous Adder for Performance Optimization

An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always in larger area occupied by circuit on chip and vice-versa. In order to design an optimized adder circuit which provides area/delay tradeoffs, we studied different available parallel, synchronous adders and proposed a new adder based on combination of them. In this paper, we proposed a new type of adder architecture known as heterogeneous adder that consists of concatenation of sub-adder (homogeneous adder) of different types. The heterogeneous adder architecture provides better design tradeoffs in terms of area and delay characteristics.

정수선형계획법을 이용한 이종가산기의 전력-지연시간곱 최적화

본 논문에서는 이종가산기구조에 근거한 이진가산기의 전력-지연시간곱의 최적화 방법론을 제안한다. 정수선형 계획법(Integer Linear Programming)에 의해 이종가산기의 전력-지연시간곱을 공식화하였다. 정수선형계획법의 사용을 위하여 최초의 전력-지연시간곱의 비선형수식을 선형수식으로 변환하는 기법을 채택하였다. 또한, 제안된 방법이 전력지연시간곱(Power-Delay Product)의 척도에서 기존가산기와 비교해 우월함을 실험결과를 통해 확인하였다.

향상된 연산시간, 회로면적, 소비전력의 절충관계를 위한 혼합가산기 기반 CORDIC

모바일 임베디드 시스템에서는 성능이 우수하면서도 작은 칩 크기와 저 전력의 동작 조건이 요구된다. CORDIC 연산기는 초월 함수들을 효율적으로 계산하는 알고리즘으로, 특유의 하드웨어 간결성으로 인하여 모바일 임베디드 시스템에 매우 적합한 연산기이다. 하지만 CORDIC 알고리즘은 내부 연산의 반복 횟수에 따라 성능이 저하되는 문제점이 있다. CORDIC 연산기를 분석하면 가산기의 영향이 매우 크다는 것을 알 수 있다. 가산기의 알고리즘 종류에 따라 필요 이상의 성능 증가로 인하여 회로 면적과 소비 전력이 증가하면서 성능이 낭비되는 문제점을 해결하기 위하여 연산 시간, 회로 면적, 소비 전력에 대한 보다 심층적인 절충 관계 분석이 필요하다. 본 논문에서는 가산기에 따른 자원 낭비를 최소화하는 방법으로 혼합 가산기를 이용한 CORDIC 연산기를 제안하고, 혼합 가산기를 사용하면 요구 조건에 보다 최적화된 CORDIC 연산기를 설계할 수 있음을 실험 결과를 이용하여 보였다. High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING

The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder.