Heat Dissipation Path Research Articles

Thermal Design of Tile Type Active Phased Array Radar Antenna

Abstract Based on the structure and heat source distribution characteristics of the tile-type active phased array radar antenna, forced air cooling is adopted for its heat dissipation design. The heat dissipation path and fins of the main heating module of the antenna were designed and calculated, and the reliability of the thermal design was verified through software simulation and thermal testing.

Calculation method of electromagnetic losses and hot-spots temperature of giant magnetostrictive transducer

Due to the complex energy conversion processes and limited avenues for heat dissipation in the giant magnetostrictive transducer (GMT). Large losses and elevated internal temperature rise are inevitable, this would bring into serious reliability problem for GMT. Accurately analyzing its electromagnetic losses and hot-spots temperature are crucial for designing and optimizing the transducer. High-power GMT typically use permanent magnet (PM) to provide a bias magnetic field for enhanced power density. Although, this structure could significantly reduce the volume of driving part, it also caused issues such as non-uniform magnetic field distribution and bias magnetic field, which have great influence on the magnetic energy loss and hot-spots temperature rise. The previous researches seldomly investigate these influences on total loss at GMT system level. Additionally, the differential excitation coil loss caused by AC resistance among multi-layers can’t be neglected, which can lead to variations in coil loss and temperature rise. Therefore, this paper proposed a detailed electromagnetic losses and hot-spots temperature rise calculation model from material level to GMT system level. This method can obtain the distribution of electromagnetic losses within multiple factors, and the hot-spots temperature rise considering the temperature non-uniform distribution. Firstly, we have developed a precise loss calculation model, which takes the influence caused by PM bias and non-uniform magnetic field on magnetic energy loss into account. Additionally, the proposed model could conclude the impact of inter-coil resistance variations on the eddy current loss in excitation coil. Secondly, based on of the non-uniform distribution of losses in driving part, using the divisional thermal modeling approach and a 2-D T-shaped equivalent thermal network, we further constructed a transient temperature calculation model for GMT. This approach can effectively improve the energy conversion efficiency of GMT, so as to enhance the thermal reliability of the transducer. Finally, a testing system for the loss-thermal of GMT was established to validate the effectiveness of proposed model. Results indicate that the average error between our loss calculation model and experimental results is 2.93%, while the corresponding error for without considering the above factors is 15.97%. This confirms the necessity of conducting a detailed electromagnetic losses calculation model. In addition, the average error of the temperature rise calculation model is less than 5%, while the error for without considering the losses distribution and heat dissipation paths difference is exceed 10%. In conclusion, our proposed method accords well with the measured results, and can provide significant fundamental for design and optimization of GMT.

Synergistic effect of positive temperature coefficient and thermally conductive micro‐nano fillers on electrical and thermal properties of epoxy resin

AbstractThis study investigates the effect of positive temperature coefficient (PTC) fillers, i.e., barium strontium titanate (BST‐60) and nano hexagonal boron nitride (h‐BN) fillers, on thermal and dielectric insulation properties of epoxy (EP). The electrical resistivity, DC breakdown strength, space charge, thermal conductivity, thermogravimetric analysis, and glass transition temperature (Tg) of EP composites were measured. Results indicate that, below curie temperature, the EP composites containing 0.5 and 1 wt% of BST and 5 wt% of h‐BN have superior electrical resistivity, breakdown strength, and thermal conductivity. However, above curie temperature, the EP composites containing 2 and 2.5 wt% of BST and 5 wt% of h‐BN have superior insulation properties than the pure EP and other composites. While the thermal properties of EP improve with an increase in h‐BN loading to 10 wt%, its dielectric properties are slightly compromised due to the presence of tiny defects in the composite material. It is hypothesized that the BST‐60 suppresses the negative temperature coefficient effect (NTC) of EP by regulating the electrical resistivity above the curie point, whereas nano h‐BN enhances the thermal conductivity of EP by constructing a heat dissipation path. The proposed mechanism for charge dynamics along with heat conduction‐dissipation explains the fillers' behavior at different temperatures.Highlights Analysis of epoxy composites with polydopamine‐modified BST and h‐BN fillers. PTC fillers are used to mitigate the negative temperature effect of epoxy. Optimal fillers wt% improves dielectric and thermal properties. This study shows that optimized epoxy composites can be used for packaging.

A graphene nanoflake-based flexible composite phase change material for enhanced heat dissipation in chip cooling

Efficient heat dissipation is a key requirement for stable performance retention and failure prevention of microelectronic components. In practical applications, the interface thermal resistance between the component and the heat dissipation unit affects the heat dissipation effect. Thermal interface materials (TIM) are used to fill the voids at the solid interface between the device and the heat sink to create a thermally conductive path for heat dissipation. Phase change materials (PCMs) are candidates as TIM for next-generation electronic devices due to their excellent latent heat storage. However, some inherent problems of PCMs, such as low thermal conductivity, high solid-state rigidity, and easy leakage, also limit their application in the thermal management of electronic equipment. This study prepared a biomass cotton cloth substrate with a woven structure attached to graphite nanosheets and further constructed a thermally conductive matrix through drying or high-temperature carbonization. Through the composite of thermally conductive matrix and paraffin wax (PW), a flexible phase change thermal interface composite material was obtained. The phase change enthalpy of composite materials is as high as 157.7 J/g. The thermal conductivity of the composite material is 293.7 % higher than that of pure PW. On its excellent flexibility and structural strength, the composite material can better adapt to the thermal interface, reduce contact thermal resistance, and thus achieve good leakage resistance. The flexible phase-change TIM developed in this study have broad application prospects in the fields of chip heat dissipation and thermal management of wearable electronic devices.

Vertically-aligned Zn2SnO4–Fe3O4 core-shell microsphere-based thermal interface material with high thermal conductivity

In this study, we successfully fabricated vertically aligned Zn2SnO4 (ZTO)-Fe3O4 core-shell microsphere (MS)-based thermal interface material (TIM) formed by an external magnetic field. The thermal conductivity of the randomly distributed ZTO-Fe3O4 core-shell/PDMS-based TIMs was enhanced with increasing loading fraction of fillers and TIM with 25 vol % fillers 2.5 times effectively reduced GPU temperature compared to bare PDMS sample. Moreover, the vertically-aligned 25 vol% ZTO-Fe3O4 core-shell filler embedded TIM additionally reduced temperature by 5.1 % and 24.1 % compared to randomly dispersed ZTO-Fe3O4 MS TIMs and bare PDMS, respectively. Experimental results showed that the ZTO-Fe3O4 TIMs can be used as high thermal conductivity TIM filler, and vertically aligned core-shell filler can maximize thermal conductivity by forming an effective thermal path from bottom to top. The theoretical analysis results obtained using COMSOL Multiphysics 5.6 simulation corresponded well with experimental ones. Our suggested vertically aligned ZTO-Fe3O4 core-shell-based TIM can provide an effective heat dissipation path for advanced semiconductor devices with a wide range of applications.

Temperature Field Calculation and Thermal Circuit Equivalent Analysis of 110 kV Core Cable Joint

In order to indirectly calculate the core temperature of a cable joint, an equivalent transient thermal circuit model of single-core cable joint by considering axial heat dissipation is proposed. Firstly, the temperature field of the middle joint of a 110 kV single-core cable is calculated by finite element method. Based on the heat dissipation path of the core, an improved equivalent thermal circuit model is proposed. The axial heat dissipation of the cable joint core is simplified to a thermal resistance and the temperature rise of the cable body core, the temperature calculation of the cable joint transient process is realized. Compared with the results of finite element simulation, the steady-state temperature errors of the thermal circuit model are within 1 °C, while the maximum temperature errors of the transient process shall not exceed 3 °C, which proves the validity of the model. This method can provide reference for temperature inversion and the dynamic current-carrying capacity prediction of cable joints.

The heat dissipation path of self-heating effects for the SOI MOSFET by considering the BOX layer and the TiN barrier layer

Silicon-on-insulator devices are widely utilized in high-performance and high-reliability fields, facing challenges from self-heating effects (SHEs). However, research on the heat dissipation path closely related to SHEs remains incomplete. This paper initiates an in-depth analysis of thermal effects involving the fine structures within the heat dissipation path, using ultrafast pulse I–V measurements combined with thermal simulations. It is found in practical processes that the SHEs of scaled-down devices decreased by 40% rather than increased. Research shows the improvement is attributed to the reduction in the thickness of the buried oxide layer between different generations of processes, and the decrease in thermal sensitivity. Based on the two-stage SHE mechanism, the study clarifies for the first time that the box layer mainly affects first-stage heat dissipation, and the main timescale of impact is about the first 100 ns. In addition, the heat dissipation contact capability can effectively affect the temperature rise of first-stage SHEs. For the first time, we reveal that the TiN barrier layer with low thermal conductivity is the key factor limiting heat dissipation through contact. This study represents the crucial step toward a comprehensive investigation of SHEs, offering substantial support for device modeling.

An Accurate Electro-Thermal Coupling Model of a GaAs HBT Device under Floating Heat Source Disturbances.

Taking into consideration the inaccurate temperature predictions in traditional thermal models of power devices, we undertook a study on the temperature rise characteristics of heterojunction bipolar transistors (HBTs) with a two-dimensional cross-sectional structure including a sub-collector region. We developed a current-adjusted polynomial electro-thermal coupling model based on investigating floating heat sources. This model was developed using precise simulation data acquired from SILVACO (Santa Clara, CA, USA). Additionally, we utilized COMSOL software (version 5.6) to simulate the temperature distribution within parallel power cells, examining further impacts resulting from thermal coupling. The research findings indicate that the rise in current induces modifications in the local carrier concentration, thereby prompting variations in the local electric field, including changes in the heat source's peak location and intensity. The device's peak temperature exhibits a non-linear trend regulated by the current, revealing an error margin of less than 1.5% in the proposed current-corrected model. At higher current levels, the drift of the heat source leads to an increase in the heat dissipation path and reduces the coupling strength between parallel devices. Experiments were performed on 64 GaAs (gallium arsenide) HBT-based power cells using a QFI infrared imaging system. Compared to the traditional temperature calculation model, the proposed model increased the accuracy by 6.84%, allowing for more precise predictions of transistor peak temperatures in high-power applications.

Enhancement performance of a diaphragm compressor in hydrogen refueling stations by managing hydraulic oil temperature

The objective of this study is to address the issue of high gas temperature for diaphragm compressors in hydrogen refueling stations, which leads to a high failure rate and low volumetric efficiency. The heat transfer between the gas and oil through the diaphragm is a significant heat dissipation path of the diaphragm compressor. This paper studies the performance of a 90 MPa diaphragm compressor used in hydrogen refueling stations by managing hydraulic oil temperature. Experimental results indicate that lowering the oil temperature can significantly improve the compressor volumetric efficiency and reduce the discharge temperature. For the test case, as the oil temperature decreases from 95 °C to 35 °C, the volumetric efficiency increases from 36.2 % to 43.5 %, and the measured discharge temperature decreases by 49 °C. This study proposes a thermodynamic simulation model for diaphragm compressors, and the simulation results agree with the experimental results. This model can be used to calculate the thermodynamic characteristics of diaphragm compressors and provide guidance to designers.

Effect of Local Substrate Removal and Backside Al Heat Dissipation Layer on GaN-on-Si Device RF Performance

This study investigates the influence of local substrate removal and the implementation of a backside Al heat dissipation layer on the radio frequency (RF) performance of GaN-on-Si devices. To optimize the RF properties of these devices by mitigating the influence of the parasitic capacitance layer between the AlN nucleation layer and the Si substrate by the local substrate removal process. Nevertheless, this removal reduces the heat dissipation path, elevating channel temperatures and reducing drain current and transconductance (GM). To address this issue, an Al heat dissipation layer is deposited onto the device’s backside surface. Combining the LSR process and the Al heat dissipation layer improved power-added efficiency from 38.93% to 48.47% at a frequency of 3.5 GHz.

Analytical thermal resistance network model for calculating each mean die temperature of the multi-chips module combined with quad flat no-leads packaging

With the rapid advancement of next-generation communication technology, traditional Quad Flat No-leads (QFN) packaging is facing challenges to meet functional requirements. Due to its high integration and excellent thermal performance, the Multi-chips Module combined with Quad Flat No-leads (MCM-QFN) packaging is gaining popularity. However, the structural complexity of MCM-QFN packaging and the thermal coupling effect between multiple dies make it challenging to analyze the steady-state thermal distribution of MCM-QFN packaging, which is necessary for assessing the reliability and optimizing the layout design of the multi-chips module. By analyzing the heat dissipation path from each die to the ambient, this paper proposes an analytical thermal resistance network model for calculating each mean die temperature of MCM-QFN packaging. The thermal coupling effect among the multi-chips, the thermal spreading resistance between critical layers, and the boundary conditions and cooling conditions are all considered. All thermal resistances in the model are expressed analytically, and the mean temperature of each chip can be calculated within 0.1 s using MATLAB programming. To validate the accuracy of the proposed model, finite element method (FEM) simulations are conducted to provide a reference for the mean temperature of each chip under four sets of thermal conditions. The data comparison demonstrates that the analytical model is fast and accurate in calculating each mean die temperature of MCM-QFN packaging, with a maximum error of 3.72%, and the calculation speed increased by about 600× compared to that of FEM simulation. Furthermore, the analytical model is able to offer a direction for optimizing the layout design and material selection of MCM-QFN packaging.

P-type trench gate based drain-extended N-type MOS design for high unclamped inductive switching reliability

The drain-extended NMOS (DeNMOS) is a low-voltage power MOSFET. It comprises intrinsic parasitic BJT (P-BJT), which can trigger under the influence of lattice heating or avalanche-generated holes. The parasitic bipolar current and self-heating effect (SHE) facilitates the second breakdown phenomena near the drain. Hence, we proposed DeNMOS with a P-type trench gate (PTG) placed between the body and source contact to optimize the P-BJT and SHE at high current conditions using the Sentaurus TCAD simulator tool. The PTG increases hole accumulation within the P-body region to optimize the bipolar effect. Furthermore, the proposed DeNMOS (PTG_DeNMOS) structure incorporates an additional heat dissipation path, improving the thermal stability of the device. It is shown that mitigating the P-BJT enhances the device avalanche ruggedness and unclamped inductive switching (UIS) reliability at high current conditions. The analyzed results show that the proposed PTG_DeNMOS ensures UIS reliability at a peak current density 35% higher than the conventional DeNMOS (C_DeNMOS) without compromising mixed signal performance.

Simultaneously improving vertical thermal conductivity and oil resistance of carbon fiber reinforced composite through layer-by-layer plasma surface treatment

Carbon fiber reinforced composite (CFRC) has attracted considerable attention as a robust high-performance material with outstanding strength-to-weight ratio and is widely used in various applications from aerospace to automotive industries. However, this composite commonly suffers from low vertical thermal conductivity and poor oil resistance, thereby limiting the applicability of lightweight CFRC in metal replacement. Here, we present a facile and effective approach to simultaneously improve vertical thermal conductivity and oil resistance of CFRC on the basis of formation of surficial and interfacial hydrophilic oxide layers in the stacked prepregs using the layer-by-layer plasma surface treatment. Thermally conductive and oil-resistant composite was achieved by simple layer-by-layer plasma surface treatment on individual prepregs and subsequent high-pressure compression of plasma-treated prepregs under elevated temperature. It is experimentally revealed that densely interlocked laminated CFRC with rough and oxidized multiple interlayers where interpenetrated oxide moieties are vertically distributed minimizes interfacial thermal resistance between stacked prepregs, thereby offering an efficient heat dissipation path in a through-thickness direction. Furthermore, the plasma-induced hydrophilic modification of both surface and interlayer endows the CFRC with excellent oil resistance. Consequently, this facile approach affords high vertical thermal conductivity and remarkable oil resistance, as well as an excellent mechanical strength. Compared to conventional CFRC, our versatile composite accomplishes excellent vertical thermal conductivity with 135% enhancement after oil absorption and outstanding oil resistance with 240% improvement.

Optimized method for thermal through silicon via placement with non-uniform heat sources in 3-D-IC

In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation-related issues have been solved in 3-D integrated circuit (3-D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3-D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip.

A combined solution of thermoelectric coolers and microchannels for multi-chip heat dissipation with precise temperature uniformity control

• Conbined TEC and microchannel cooling proposed for multi-chip heat dissipation. • Based on the change of applied current, the equivalent thermal resistance of TEC is changed to realize the active temperature control of chip. • Heat dissipation with temperature uniformity control of multi-chip combined cooling is studied. Effective thermal management with precise temperature uniformity is necessary to improve the performance and stability of multi-chip devices such as active phased array antennas, semiconductor laser radar systems, and light emitting diode (LED) arrays. This study proposes a combined solution for multi-chip devices heat dissipation that integrates thermoelectric coolers (TECs) and microchannel heat sink to tune the temperature of each chip dynamically by controlling multiple TEC currents independently. The equivalent variable thermal resistance of the TEC can be dynamically adjusted under different TEC currents, thereby realizing the equivalent thermal resistance value of TECs change on the heat dissipation path of different chips and the precise temperature control and continuity at desired temperature range. A simplified thermal resistance network of multi-chip is established to illustrate the dynamic control mechanism of multi-chip temperature uniformity based on the variable thermal resistance. Not only the heat dissipation and temperature control of single chip under different operating conditions (TEC current, flow rate, and heat flux), but also the temperature uniformity control of multi-chip is studied. The combined cooling scheme is compared and analyzed with the microchannel cooling. The results show that this combined cooling scheme can achieve precise temperature control of multiple chips with maximum temperature difference less than 0.3 °C and temperature standard deviation less than 0.07 °C, which is far less than the maximum temperature difference of 7.89 °C and temperature standard deviation of 3.55 °C when the heat flux is 50 W/cm 2 . This represents a feasible solution for the realization of precise temperature uniformity and dynamic temperature control in multi-chip devices.

Performance tests of dual-phase CO2 cooling for particle detectors

Evaporative CO2 cooling is becoming a popular cooling solution for large-scale, high-energy particle detectors, such as the new ATLAS Inner Tracker (ITk) for the high-luminosity upgrade of the LHC. CO2 offers a high latent heat transfer at reasonable flow parameters and is an environment friendly alternative to many other coolants currently used. This cooling technique is used to investigate the thermal performance of prototypes from the ITk strip detector produced at DESY. The strip end-cap local support structure, called petal core, is designed to allow a good heat transfer between silicon strip modules glued on its surface and the embedded titanium cooling pipe. Studies on the thermal properties using infrared thermography have been performed to analyse the heat dissipation path which allows also to detect eventual imperfections in the assembly as part of the quality control strategy. A similar analysis was executed on a petal loaded with electrical modules to study the heat generation due to active components and its dissipation for each module under different CO2 conditions.

Reliability Analysis of Large-Area, Low-Pressure-Assisted Silver Sintering for Medium-Voltage Power Modules

Multi-layer insulating ceramic substrates can enable medium-voltage (MV) power modules with reduced peak electric field. This benefit is particularly important for MV silicon carbide (SiC) MOSFETs due to their higher operating voltages. Large-area, low-pressure-assisted silver sintering is a potential solution for bonding substrates to create a multi-layer structure. The voiding content and defect density of the bond used to create the multi-layer substrate stack-up are critical to the reliability of the power module and thermal performance, as this bond is in the primary path for heat dissipation in the power module structure. Samples of two-layer direct bonded aluminum (DBA) stacks have been fabricated and subjected to thermal cycling to analyze their reliability. Passive thermal cycling from −40 °C to 200 °C was performed. Cross sections were cut at pre-determined intervals and imaged with scanning electron microscopy (SEM). After 1000 thermal cycles, adhesive failures are observed between the sintered silver and DBA surface. Cross sections were cut and imaged via optical microscope and SEM. Thermal analyzer measurements are recorded on a 10-kV SiC power module using the sintered DBA substrate stacks.

TB-NUCA: A Temperature-Balanced 3D NUCA Based on Bayesian Optimization

Three-dimensional network-on-chip (NoC) is the primary interconnection method for 3D-stacked multicore processors due to their excellent scalability and interconnect flexibility. With the support of 3D NoC, 3D non-uniform cache architecture (NUCA) is commonly used to organize the last-level cache (LLC) due to its high capacity and fast access latency. However, owing to the layered structure that leads to longer heat dissipation paths and variable inter-layer cooling efficiency, 3D NoC experiences a severe thermal problem that has a big impact on the reliability and performance of the chip. In traditional memory-to-LLC mapping in 3D NUCA, the traffic load in each node is inconsistent with its heat dissipation capability, causing thermal hotspots. To solve the above problem, we propose a temperature-balanced NUCA mapping mechanism named TB-NUCA. First, the Bayesian optimization algorithm is used to calculate the probability distribution of cache blocks in each node in order to equalize the node temperature. Secondly, the structure of TB-NUCA is designed. Finally, comparative experiments were conducted under random, transpose-2, and shuffle traffic patterns. The experimental results reveal that, compared with the classical NUCA mapping mechanism (S-NUCA), TB-NUCA can increase the mean-time-to-failure (MTTF) of routers by up to 28.13% while reducing the maximum temperature, average temperature, and standard deviation of temperature by a maximum of 4.92%, 4.48%, and 20.46%, respectively.

Electromagnetic Simulation and Realization of MCM GaAs MMICs Based Packaging for High Gain (40 dB) and High-Power (33dBm) Transmitter Applications

This paper details the development of high thermal conductivity (395 W/mK) metal package which is suitable for high-gain and high-power multi-chip modules (MCM). This package is designed using thermal analysis data to meet the long-term reliability. Thermal modeling was done to estimate the thermal resistance and design of package made to minimize the thermal resistance in the heat dissipation path. It is a dual cavity structure MCM suitable for packaging GaAs-based MMICs working up to Ku-Band. This is a two-cavity package with dimensions 17.2 mm×10 mm×3.5 mm and they are internally separated cavities to handle the high gain and power, and the same package 3D EM simulation is done in CST studio 2016. This modeled package is optimized and fabricated by using copper material to meet the thermal management requirements of a power amplifier operated in CW mode. The S-parameter measurements were carried out over broadband also but considered over 6–18 GHz and test parameters resulted in typical S21 of 40 dB, S11 of 10 dB, S22 of 5 dB, and output power of 33 dBm. Thermal analysis is carried out using thermalyze software for analyzing the rise in junction temperature during DC biasing conditions and to calculate the necessity of junction cooling to get the highest output power. Temperatures at three stages are 100.13, 99.85 and 83.38 °C with the base plate maintained at a constant temperature of 60 °C. Further, studies carried out on different base materials for good heat flow and CTE match with GaAs dies as copper tungsten and copper–molybdenum copper.

An optimization method of temperature field distribution to improve the accuracy of laser multi-degree-of-freedom measurement system

ObjectiveAiming at the problem that the accuracy and stability of laser multi-degree-of-freedom measurement systems (MDFM) were affected by temperature, an optimization method of temperature field distribution was proposed. MethodsWe analyzed the rotation matrix of optical components and established a measurement error model of misalignment caused by temperature variation. We established the thermal model of the transmitter and optimized the heat dissipation path. The thermal resistance of key components was optimized by computational fluid dynamics (CFD) analysis. ResultsThe simulation results showed that the highest temperatures of the optimized circuit and inner shell were reduced by 8.91 ℃ and 1.20 ℃. The experimental results showed that the temperatures of the optimized circuit and inner shell were reduced by 7.85 ℃ and 0.27 ℃. When the ambient temperature was 20 ℃, the measurement accuracy of pitch angle and vertical straightness were increased by 36.41% and 58.60%. When the ambient temperature was 25 ℃, the measurement accuracy were increased by 16.36% and 36.16%. ConclusionThe optimization method of temperature field distribution can effectively improve the measurement accuracy and stability of the MDFM.