Header Error Control Research Articles

A method of improving misframe for HEC‐based variable length frame suitable for IP services

AbstractAs the layer 2 technology for transfer of the IP packet, a variable length frame has been proposed in which the HEC (Header Error Control) and the frame length are defined in the header. In this paper, it is shown with regard to these HEC‐based variable length frames that the phenomenon of misframing is likely, in which a hunt state appears by mistake due to frame error. As a method for improvement, a forced 2‐bit error correction method is proposed. The performance of the proposed method is clarified and the sufficient characteristic is demonstrated. In addition, from the point of view of reframe time and false frame probability, the order of the generating polynomial of CRC optimum for HEC and the backside protection stage number are presented. From a similar viewpoint, it is shown quantitatively that the error detection is superior to the error correction with regard to CRC operation in the hunt state and pre‐sync state. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 86(6): 46–58, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.10018

Microprocessor adapter for ATM networks

This paper presents a microprocessor adapter for ATM networks. Its transmission functions, which are related to the upstream direction, include cell buffering, header error control, cell assembling, rate coupling, and information insertion. The reception functions, which are related to the downstream direction, include information extraction, rate decoupling, cell buffering, header error detection and correction, cell delineation, connection identity fields extraction and identification, cell disassembling and classification, and idle cell discarding. The transmission direction can be supported optionally by a traffic shaper, which is responsible for adapting emitted traffic to ATM network. The microprocessor adapter, which can be used in terminals or in interworking units and switches, implements basic functions of the lower layers of the ATM protocol reference model. It uses three applications specific integrated circuit (ASIC) chips. The three chip-set and other logic can been used to develop a personal computer (PC) adapter for ATM networks. This PC adapter offers bulk data transfer across the ATM network, internet applications over TCP/IP, interactive applications, LAN–ATM interworking facilities using a PC as a router, multimedia and other services.

Mechanism for shaping the emitted traffic at ATM terminal‐points

AbstractA mechanism for controlling the emitted traffic to asynchronous transfer mode (ATM) network, system design and implementation architectures are introduced. Specifically, the effective rate of a stream, defined under certain multiplexing conditions and quality‐of‐service specifications, is enforced to desired values by controlling the cell emission rate of the generated bursts. The traffic shaping mechanism is closely associated to an ATM transmitter, which is mainly responsible for ATM cell assembly and header error control. The mechanism has been designed to support data communication services. The whole system has been implemented as a VLSI circuit. Copyright © 2002 John Wiley & Sons, Ltd.

A transceiver circuit for ATM networks

This paper presents a transceiver digital circuit. The circuit is responsible for the emission of packets to the asynchronous transfer mode (ATM) network as well as for the manipulation of received ATM packets belonging to virtual connections. It has been designed to support data communication services. The circuit, which can be used in terminals or in interworking units and switches, implements basic functions of the lower layers of the ATM protocol reference model. The transmission functionality includes cell buffering, header error control, cell assembling, rate coupling and information insertion. The receiver realizes information extraction, rate decoupling, cell buffering, header error detection and correction, connection identity fields extraction and identification, cell disassembling and classification, and idle cell discarding functions. The circuit has been implemented on applications specific integrated circuit (ASIC) chips.

Header error control schemes for coping with upstream channel noise in the HFC network

Header error control schemes for coping with upstream channel noise in the HFC network

Optical implementation of asynchronous-transfer-mode header-error control

The asynchronous transfer mode (ATM) is a promising technique for broadband switching that is capable of supporting high-bit-rate multimedia services. Progress in all-optical parallel processing shows that photonics may be used in the future in full-functionality ATM switching nodes. All-optical switching fabrics and buffers have already been demonstrated. Fewer studies have been dedicated to ATM header-processing functions. As an example of photonic header processing, the implementation of a header-error control (HEC) subsystem by means of an optical circuit is investigated. Although traditional electronic decoders perform HEC in a serial mode, the architecture chosen for the optical HEC subsystem is based on parallelism, and an appropriate parallel-decoding algorithm was used in designing it.

Error correction and error detection techniques for wireless ATM systems

Error correction and error detection techniques are often used in wireless transmission systems. The Asynchronous Transfer Mode (ATM) employs Header Error Control (HEC). Since ATM specifications ha...

A recommended error control architecture for ATM networks with wireless links

This paper provides performance results through analysis and simulation for key error control problems encountered in using wireless links to transport asynchronous transfer mode (ATM) cells. Problems considered include the forward-error correction (FEC) and interleaving at the physical layer, the impact of wireless links on the ATM cell header-error control (HEC) sand cell delineation (CD) functions, the application of data link automatic repeat-request (ARQ) for traffic requiring reliable transport, and the impact of the choice of end-to-end ARQ protocol for reliable service. We conclude that it is very important to make the physical layer as SONET-like as possible through the use of powerful FEC, interleaving, and ARQ. These additional error control measures are especially necessary for disturbed channels because of the degrading effects of the channel on higher-layer functions. A recommended error control architecture is given with tradeoffs.

Cell discard and TDMA synchronization using FEC in wireless ATM systems

The asynchronous transfer mode (ATM) employs header-error control (HEC) to protect the ATM cell header from bit error and/or avoid the misforwarding of ATM cells. However, wireless ATM systems require a more powerful forward-error correction (FEC) scheme to offer acceptable bit-error rate (BER) performance. This paper proposes the utilization of FEC, which makes it possible to discard ATM cells more reliably. Time-division multiple-access (TDMA) is very suitable for wireless ATM systems. In the TDMA scheme, synchronization is very important. This paper also proposes to combine FEC with unique word (UW) detection for improving TDMA synchronization characteristics.

Implementation issues of the ATM cell delineationmechansim

The cell delineation mechanism (CDM) used in the asynchronous transfer mode (ATM) interfaces is based on the validation of the header error control (HEC) byte of the incoming cells, and is used for extracting the boundaries of the incoming cell stream. The CDM is analysed and an efficient implementation algorithm is derived, resulting in a hardware architecture, applicable at high data rates.