In this paper, ESD improvements of an output driver that driving a large current in DC brushless fan ICs under HBM ESD stress is investigated. In order to improve ESD robustness, some protection blocks will be designed and implemented by the layout parameters and structures tuning. From the preliminary ESD testing result, it was found that the positive Pad-to-VSS (PS) zapping mode of the original DUT is weakest for the output driver of DC brushless fan ICs during an HBM zapping. After a systematic improvement, it is found that the FOD structure of adding protection circuits can effectively protect the whole-chip ESD damage, as compared with the original DUT; the values of ESD failure threshold (VESD) are increased > 57%, which allows output driver devices more robust in the ESD immunity.