Single-phase ac to dc converters for computers and related applications have requirements that are difficult to meet while achieving both high power density and high efficiency: wide input voltage range, large voltage step down, galvanic isolation, harmonic current limits and hold-up requirements. This work explores a circuit architecture and topology that is structured to facilitate operation at multi-MHz frequencies in order to address this challenge. We present a 250 W, 24 V output, universal input PFC converter prototype that leverages the proposed approach to achieve a power density of 34.9 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> while meeting the 80 PLUS Platinum efficiency standard, EN61000-3-2 line harmonic requirements and half-cycle holdup. The converter operates at variable switching frequencies in the range of 1-4 MHz; the measured efficiency at 230 Vac RMS, 60 Hz input is 95.33% at full load and 84.57% at 8% load.
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