Transactional Memory Research Articles

Metaverse-based distance learning as a transactional distance mitigator and memory retrieval stimulant

This present study explores Metaverse-based Distance Learning (MDL) as a mitigative strategy of transactional distance (TD) and an enhancer of memory retrieval in an educational setting. We conducted two experimental studies. In the first study (n = 367 participants), we found that MDL significantly reduced perceived TD, leading to positive learner attitudes and increased intentions for repeat learning. The second study utilized functional Near-Infrared Spectroscopy (fNIRS) to assess hemodynamic responses in the prefrontal cortex of 30 participants, comparing brain activity during lectures in MDL and e-learning environments. Results indicated that MDL elicited higher oxy-Hb activation in the prefrontal cortex, particularly during cognitively challenging tasks, correlating with improved memory retrieval. Grounded in both Transactional Distance Theory (TDT) and context-dependent memory (CDM) frameworks, we found that the technological and educational potential of MDL not only reduces psychological barriers in distance learning but also shows how it can improve cognitive engagement and retention. These findings underscore the potential of MDL in distance education and suggest pathways for future research to explore its implications further, particularly in conjunction with other emerging technologies.

Blockchain with secure data transactions and energy trading model over the internet of electric vehicles

The rise of Electric Vehicles (EVs) has introduced significant advancement and evolution in the electricity market. In smart transportation, the EVs have earned more popularity because of its numerous benefits including lower carbon footprints, higher performance, and sophisticated energy trading mechanisms. These potential benefits have resulted in widespread EV adoption across the world. Despite its benefits, energy management remains the biggest challenge in EVs and it is mainly because of the lack of Charging Stations (CSs) near EVs. This creates a demand for an effective, secure and reliable energy management framework for EVs. This study presents a secure data and energy trade paradigm based on Blockchain (BC) in the Internet of EVs (IoEV). BC technology prepares for the high volume of EV integration that serves as the foundation for the next generation, and to assist in developing unique privacy-protected BC-based D-Trading and storage Models. Entities evaluated for the proposed model include Trusted Authority (TA), Vehicles, Smart Meters, Roadside Units (RSU), BC, and Inter-Planetary File System (IPFS). In addition, E-trading involves several phases, including the acquiring E-trading demand requests, E-trading response requests, request matching and token assignment. Moreover, account mapping is performed using a Mayfly Pelican Optimization Algorithm (MPOA), which is created by merging the Mayfly Algorithm (MA) and Pelican Optimization Algorithm (POA). Various security features are used to protect data and energy trade in IoEV, including encryption, hashing, polynomials, and others. The testing results revealed that the MPOA outperformed the state-of-the-art results regarding memory consumption, trading rate, transaction cost, and trading energy volume with values of 4.605 MB, 91%, 0.654, and 90 kW, respectively.

A verified durable transactional mutex lock for persistent x86-TSO

AbstractThe advent of non-volatile memory technologies has spurred intensive research interest in correctness and programmability. This paper addresses both by developing and verifying a durable (aka persistent) transactional memory (TM) algorithm, $$\text {dTML}_{\text {Px86}}$$ dTML Px86 . Correctness of $$\text {dTML}_{\text {Px86}}$$ dTML Px86 is judged in terms of durable opacity, which ensures both failure atomicity (ensuring memory consistency after a crash) and opacity (ensuring thread safety). We assume a realistic execution model, Px86, which represents Intel’s persistent memory model and extends the Total Store Order memory model with instructions that control persistency. Our TM algorithm, $$\text {dTML}_{\text {Px86}}$$ dTML Px86 , is an adaptation of an existing software transactional mutex lock, but with additional synchronisation mechanisms to cope with Px86. Our correctness proof is operational and comprises two distinct types of proofs: (1) proofs of invariants of $$\text {dTML}_{\text {Px86}}$$ dTML Px86 and (2) a proof of refinement against an operational specification that guarantees durable opacity. To achieve (1), we build on recent Owicki–Gries logics for Px86, and for (2) we use a simulation-based proof technique, which, as far as we are aware, is the first application of simulation-based proofs for Px86 programs. Our entire development has been mechanised in the Isabelle/HOL proof assistant.

Using hardware-transactional-memory support to implement speculative task execution

Loops take up most of the time of computer programs, so optimizing them so that they run in the shortest time possible is a continuous task. However, this task is not negligible; on the contrary, it is an open area of research since many irregular loops are hard to parallelize. Generally, these loops have loop-carried (DOACROSS) dependencies and the appearance of dependencies could depend on the context. Many techniques have been studied to be able to parallelize these loops efficiently; however, for example in the OpenMP standard there is no efficient way to parallelize them. This article presents Speculative Task Execution (STE), a technique that enables the execution of OpenMP tasks in a speculative way to accelerate certain hot-code regions (such as loops) marked by OpenMP directives. It also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for executing tasks speculatively and describes a careful evaluation of the implementation of STE using HTM on modern machines. In particular, we consider the scenario in which speculative tasks are generated by the OpenMP taskloop construct (Speculative Taskloop (STL)). As a result, it provides evidence to support several important claims about the performance of STE over HTM in modern processor architectures. Experimental results reveal that: (a) by implementing STL on top of HTM for hot-code regions, speed-ups of up to 5.39× can be obtained in IBM POWER8 and of up to 2.41× in Intel processors using 4 cores; and (b) STL-ROT, a variant of STL using rollback-only transactions (ROTs), achieves speed-ups of up to 17.70× in IBM POWER9 processor using 20 cores.

Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources

FPGAs are increasingly popular in cloud environments for their ability to offer on-demand acceleration and improved compute efficiency. Providers would like to increase utilization, by multiplexing customers on a single device, similar to how processing cores and memory are shared. Nonetheless, multi-tenancy still faces major architectural limitations including: (a) inefficient sharing of memory interfaces across hardware tasks (HT) exacerbated by technological limitations and peculiarities, (b) insufficient solutions for performance and data isolation and high quality of service, and (c) absent or simplistic allocation strategies to effectively distribute external FPGA memory across HT. This article presents a full-stack solution for enabling multi-tenancy on FPGAs. Specifically, our work proposes an intra-fpga virtualization layer to share FPGA interfaces and its resources across tenants. To achieve efficient inter-connectivity between virtual FPGAs (vFGPAs) and external interfaces, we employ a compact network-on-chip architecture to optimize resource utilization. Dedicated memory management units implement the concept of virtual memory in FPGAs, providing mechanisms to isolate the address space and enable memory protection. We also introduce a memory segmentation scheme to effectively allocate FPGA address space and enhance isolation through hardware-software support, while preserving the efficacy of memory transactions. We assess our solution on an Alveo U250 Data Center FPGA Card, employing 10 real-world benchmarks from the Rodinia and Rosetta suites. Our framework preserves the performance of HT from a non-virtualized environment, while enhancing the device aggregate throughput through resource sharing; up to 3.96x in isolated and up to 2.31x in highly congested settings, where an external interface is shared across four vFPGAs. Finally, our work ensures high-quality of service, with HT achieving up to 0.95x of their native performance, even when resource sharing introduces interference from other accelerators.

Ordered scheduling in control-flow distributed transactional memory

Consider the control-flow model of transaction execution in a distributed system modeled as a communication graph where shared objects positioned at nodes of the graph are immobile but the transactions accessing the objects send requests to the nodes where objects are located to read/write those objects. The control-flow model offers benefits to applications in which the movement of shared objects is costly due to their sizes and security purposes. In this paper, we study the ordered scheduling problem of committing dependent transactions according to their predefined priorities in this model. The considered problem naturally arises in areas, such as loop parallelization and state-machine-based computing, where producing executions equivalent to a priority order is needed to satisfy certain properties. Specifically, we study ordered scheduling considering two performance metrics fundamental to any distributed system: (i) execution time - total time to commit all the transactions and (ii) communication cost - the total distance traversed in accessing required shared objects. We design scheduling algorithms that are individually or simultaneously efficient for both the metrics and rigorously evaluate them through several benchmarks on random and grid graphs, validating their efficiency. To our best knowledge, this is the first study of ordered scheduling in the control-flow model of distributed transaction execution.

Novel adaptive quantization methodology for 8-bit floating-point DNN training

There is a high energy cost associated with training Deep Neural Networks (DNNs). Off-chip memory access contributes a major portion to the overall energy consumption. Reduction in the number of off-chip memory transactions can be achieved by quantizing the data words to low data bit-width (E.g., 8-bit). However, low-bit-width data formats suffer from a limited dynamic range, resulting in reduced accuracy. In this paper, a novel 8-bit Floating Point (FP8) data format quantized DNN training methodology is presented, which adapts to the required dynamic range on-the-fly. Our methodology relies on varying the bias values of FP8 format to fit the dynamic range to the required range of DNN parameters and input feature maps. The range fitting during the training is adaptively performed by an online statistical analysis hardware unit without stalling the computation units or its data accesses. Our approach is compatible with any DNN compute cores without any major modifications to the architecture. We propose to integrate the new FP8 quantization unit in the memory controller. The FP32 data from the compute core are converted to FP8 in the memory controller before writing to the DRAM and converted back after reading the data from DRAM. Our results show that the DRAM access energy is reduced by 3.07×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes $$\\end{document} while using an 8-bit data format instead of using 32-bit. The accuracy loss of the proposed methodology with 8-bit quantized training is ≈1%\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\approx 1\\%$$\\end{document} for various networks with image and natural language processing datasets.

Memory-efficient neurons and synapses for spike-timing-dependent-plasticity in large-scale spiking networks.

This paper addresses the challenges posed by frequent memory access during simulations of large-scale spiking neural networks involving synaptic plasticity. We focus on the memory accesses performed during a common synaptic plasticity rule since this can be a significant factor limiting the efficiency of the simulations. We propose neuron models that are represented by only three state variables, which are engineered to enforce the appropriate neuronal dynamics. Additionally, memory retrieval is executed solely by fetching postsynaptic variables, promoting a contiguous memory storage and leveraging the capabilities of burst mode operations to reduce the overhead associated with each access. Different plasticity rules could be implemented despite the adopted simplifications, each leading to a distinct synaptic weight distribution (i.e., unimodal and bimodal). Moreover, our method requires fewer average memory accesses compared to a naive approach. We argue that the strategy described can speed up memory transactions and reduce latencies while maintaining a small memory footprint.

CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory

CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory

On the interactions between ILP and TLP with hardware transactional memory

Hardware implementations of Transactional Memory (HTM) are designed to facilitate efficient thread synchronization in parallel programs, encouraging the use of larger critical sections. By employing optimistic concurrency control to execute transactions speculatively, HTM systems promise to deliver the performance benefits typically associated with fine-grained locks. In doing so, HTM systems must deal with transaction aborts. While under certain conditions aborts may be caused by the inherent limitations of hardware structures employed to implement TM (e.g., caches), conflicting concurrent accesses to shared memory locations are generally the prevailing cause for squashing the work done by a transactionIn this study, we present what we believe to be, to the best of our knowledge, the first characterization of how the aggressiveness of processor cores, particularly their ability to exploit instruction-level parallelism (ILP), interacts with the support for optimistic thread-level speculation offered by HTM systems. We have observed that by adjusting the size of structures that facilitate out-of-order and speculative execution, the number of aborts in the execution of transactional workloads can be altered in best-effort HTM implementations. Our findings indicate that in scenarios with high contention, a smaller number of powerful cores is more suitable, whereas in low contention scenarios, using a larger number of less aggressive cores is preferable. In addition, HTM systems that employ lazy detection and those employing eager detection with requester-stalls resolution, benefit from using simpler cores. In conclusion, abort ratios can be reduced with a careful choice of both processor aggressiveness and design aspects for each application depending on its contention.

Tile-based Multi-core Processor with Transactional Memory for Efficient Resource Utilization

Tile-based Multi-core Processor with Transactional Memory for Efficient Resource Utilization

Compiler‐driven approach for automating nonblocking synchronization in concurrent data abstractions

SummaryThis paper presents an extended version of our previous work on using compiler technology to automatically convert sequential C++ data abstractions, for example, queues, stacks, maps, and trees, to concurrent lock‐free implementations. A key difference between our work and existing research in software transactional memory (STM) is that our compiler‐based approach automatically selects the best state‐of‐the‐practice nonblocking synchronization method for the underlying sequential implementation of the data structure. The extended material includes a broader collection of the state‐of‐the‐practice lock‐free synchronization techniques, additional formal correctness proofs of the overall integration of the different synchronizations in our system, and a more comprehensive experimental study of the integrated techniques. We evaluate our compiler‐generated nonblocking data structures both by using a collection of micro‐benchmarks, including the Synchrobench suite, and by using a multi‐threaded application Dedup from PARSEC. Our automatically synchronized code attains performance competitive to that of concurrent data structures manually‐written by experts and much better performance than heavier‐weight support by STM.

Authenticity, and Approval Framework for Bus Transportation Based on Blockchain 2.0 Technology

The intelligent transport system (ITS) has transformed urban transportation, enhancing daily commutes with services like congestion management, vehicle crash prevention, traffic control, roadside safety, breakdown assistance, ticket booking, vehicle registration, and insurance. However, in urban bus transportation, the ITS faces security threats, such as data forgery and manipulation. To counter these challenges, a blockchain-based framework for bus transportation approval is proposed, ensuring data integrity and security. The framework’s performance is evaluated based on processing time, central processing unit (CPU), graphical processing unit (GPU), cloud usage, and memory consumption, and compared to Ethereum and Aurora testnet, in terms of gas cost, security, and performance. Stochastic algorithms, including the genetic algorithm and Tabu search, are used for time complexity analysis, to obtain an optimized solution. The decision-making trial and evaluation laboratory (DEMATEL) analysis is also performed to assess factors like transaction costs, execution time, memory consumption, and security. The results show that execution time, memory consumption, and processing time are crucial, while transaction cost, reliability, and transparency positively impact the system’s effectiveness. By reducing the risk of false data presentation and ensuring accurate records, the proposed framework contributes to a more efficient and reliable transportation system.

Accelerating block lifecycle on blockchain via hardware transactional memory

The processing of block lifecycles is essential to the efficiency of a blockchain, which consists of four steps: creation, execution, consensus, and validation. The permissionless blockchain systems typically had very limited transaction throughput because of the performance bottleneck of consensus protocols. With recent advances in consensus protocols, the execution and validation of transactions have become the new performance bottleneck.We propose a novel framework, called FastBlock, to speed up the execution and validation steps by introducing fine-grained concurrency. Our early design of FastBlock supported three key modules: (1) a symbolic execution-based analyzer that automatically identifies minimal atomic sections in each transaction; (2) a concurrent execution step that executes possibly conflicting transactions in parallel using hardware transactional memory; (3) a concurrent validation step that introduces a happen-before relation to deterministically re-execute transactions.The improved FastBlock presented in this article supports the nonce mechanism to schedule concurrent transactions from the same account. Moreover, we empirically study the impact of concurrency on Ethereum except for performance and shed light on potential optimizations of FastBlock. Finally, we implemented FastBlock and then evaluated the performance of FastBlock. Our result shows that the FastBlock outperforms state-of-art solutions significantly in performance: the execution step and validation step speed up to 3.0x and 2.3x on average over the original serial model, respectively, with eight concurrent threads. In addition, we evaluated the impact of the nonce mechanism, and the result shows that the performance loss caused by this mechanism is acceptable in practice.

Flexible scheduling of transactional memory on trees

We study the efficiency of executing transactions in a distributed transactional memory system. The system is modeled as a static network with the topology of a tree. Contrary to previous approaches, we allow the flexibility for both transactions and their requested objects to move simultaneously among the nodes in the tree. Given a batch of transactions and shared objects, the goal is to produce a schedule of executing the transactions that minimizes the cost of moving the transactions and the objects in the tree. We consider both techniques for accessing a remote object with respect to a transaction movement. In the first technique, instead of moving, transactions send control messages to remote nodes where the requested objects are gathered. In the second technique, the transactions migrate to the remote nodes where the objects are gathered to access them. When all the transactions use a single object, we give an offline algorithm that produces optimal schedules for both techniques. For the general case of multiple objects per transaction, in the first technique, we obtain a schedule with a constant-factor approximation of optimal. In the second technique, with transactions migrating, we give a k factor approximation where k is the maximum number of objects per transaction.

Vector-logic computing for faults-as-address deductive simulation

The aim of the research is to create logic-free vector computing, leveraging read-write transactions in memory, to solve the problems of modeling and simulation stuck-at-fault combinations for complex logic elements and digital structures. At the same time, the problem of creating smart data structures based on logical vectors, truth tables, and deductive matrices is considered to simplify algorithms for parallel stuck-at-fault simulation. Vector computing is a computational process based on read-write transactions on bits of a binary vector of functionality, where the input data and faults are the addresses of the bits. A method for the synthesis of deductive vectors for propagating input fault lists is proposed, which has a quadratic computational complexity of read-write transactions. Deductive vectors, combined into a quadratic matrix, represent explicit data structures for parallel simulation of single and multiple stuck-at-faults. The initial information for constructing a deductive matrix is a logical vector and a bit-recoding matrix. Matrix is easily obtained using a recursive procedure based on the combinatorial properties of the truth table. Considering emerging trends, focused on in-memory computing, an algorithm for fault, as addresses, simulation is proposed, using logical and deductive vectors placed in memory. The simulation algorithm is proposed not to use commands of powerful processors.

OpenCL-accelerated first-principles calculations of all-electron quantum perturbations on HPC resources.

We have proposed, for the first time, an OpenCL implementation for the all-electron density-functional perturbation theory (DFPT) calculations in FHI-aims, which can effectively compute all its time-consuming simulation stages, i.e., the real-space integration of the response density, the Poisson solver for the calculation of the electrostatic potential, and the response Hamiltonian matrix, by utilizing various heterogeneous accelerators. Furthermore, to fully exploit the massively parallel computing capabilities, we have performed a series of general-purpose graphics processing unit (GPGPU)-targeted optimizations that significantly improved the execution efficiency by reducing register requirements, branch divergence, and memory transactions. Evaluations on the Sugon supercomputer have shown that notable speedups can be achieved across various materials.

Solving task management conflict in hotel establishments through knowledge management tools: effects on innovation capabilities

PurposeThis paper aims to analyze factors based on organizational knowledge management (KM; transactional memory systems and knowledge-oriented leadership [K-OL]) that help firms to mitigate conflicts based on task management at work, with the aim to improve their innovation capabilities (IC). The knowledge-based view of the firm, conflict management theory and cognitive collective engagement theory have been used to build a model of relationships that connects the development of positive KM contexts and management of dysfunctional conflict with IC improvement.Design/methodology/approachData survey collected from inland hotel establishments in Spain is used to test seven hypotheses by means of structural equations modeling, applying the partial least squares technique. Direct, indirect and mediating relationships between variables are examined from the structural path model.FindingsThe results confirm that, as expected, IC improve when K-OL and transactive memory systems (TMSs) are properly implemented by hotel establishments, which leads them to reduce negative effects of task management conflict (TMC). Significant direct effects are found between the key variables of the study and also a significant indirect effect between K-OL and IC through TMS reinforcement and the mitigation of TMC.Practical implicationsThis paper provides useful ideas for hotel managers about how to improve KM contexts in their establishments while avoiding TMC. Efforts devoted to creating those contexts by hotel establishments are shown to be effective to improve their IC and create competitive advantages.Originality/valueThe analysis of IC improvement by studying TMC mitigation had not been researched to date by the KM literature. The consideration and testing of a model that integrates KM-related tools such as K-OL and TMS to avoid TMC in the hotel industry is the main contribution of this study.

The impact of social media usage on expertise coordination and team creative performance in distributed agile software development

PurposeThis article explores how the social media usage affect team creative performance via transactive memory system, knowledge interaction and expertise coordination.Design/methodology/approachThe study is based on the perspective of transaction memory system and expertise coordination theory. A research model was constructed and tested, involving 289 individuals from 67 distributed agile software development teams.FindingsThe results indicate that social media usage is positively correlated with transactive memory system, and social media usage and transactive memory system have positive relations to knowledge interaction and expertise coordination. Moreover, this analysis shows that knowledge interaction has a positive relationship with expertise coordination, and expertise coordination positively affects team creative performance. However, knowledge interaction has no direct relationship on team creative performance, and its indirect impact on team creative performance was fully mediated by expertise coordination. This research shows that social media usage by distributed agile software development teams can support the development of transactive memory system and promote expertise coordination. In addition, knowledge interaction alone is not enough, and expertise coordination must be achieved to increase team creative performance.Originality/valueFirst, this paper explores the mechanism of transactive memory system in distributed Agile Software Development teams from the perspective of social media, which is different from the previous information processing theory framework that confined transactive memory system to the cognitive aspects of knowledge coding, storage and retrieval. Second, this research focuses on the knowledge interaction and expertise coordination formed by team members in the process of communication in the context of social media usage, which confirms the crucial roles of social media usage and transactive memory system in team knowledge management and team creative performance. Then, this research also shows that the development of transactive memory system in the team is indeed an important factor to promote knowledge interaction and professional expertise coordination.

Toward Memory in a DNA Brush: Site-Specific Recombination Responsive to Polymer Density, Orientation, and Conformation.

Site-specific recombination is a cellular process for the integration, inversion, and excision of DNA segments that could be tailored for memory transactions in artificial cells. Here, we demonstrate the compartmentalization of cascaded gene expression reactions in a DNA brush, starting from the cell-free synthesis of a unidirectional recombinase that exchanges information between two DNA molecules, leading to gene expression turn-on/turn-off. We show that recombination yield in the DNA brush was responsive to gene composition, density, and orientation, with kinetics faster than in a homogeneous dilute bulk solution reaction. Recombination yield scaled with a power law greater than 1 with respect to the fraction of recombining DNA polymers in a dense brush. The exponent approached either 1 or 2, depending on the intermolecular distance in the brush and the position of the recombination site along the DNA contour length, suggesting that a restricted-reach effect between the recombination sites governs the recombination yield. We further demonstrate the ability to encode the DNA recombinase in the same DNA brush with its substrate constructs, enabling multiple spatially resolved orthogonal recombination transactions within a common reaction volume. Our results highlight the DNA brush as a favorable compartment to study DNA recombination, with unique properties for encoding autonomous memory transactions in DNA-based artificial cells.