Hardware-software Co-design Approach Research Articles

Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain

In this paper a new encryption system has been designed and implemented for real-time speech transmission to reduce bandwidth requirements, increase security and minimize residual intelligibility. To guarantee robustness and lightweight computation, the developed cryptosystem has been carried out in the wavelet transform domain based on a hyperchaotic model to generate mask and permutation keys. The cryptographic system has been designed using a hardware-software (HW/SW) co-design approach by developing several IP-cores in a relatively short development time. The performances and security evaluation of the system have been validated through simulation results followed by an experimental validation through the implementation of an encrypted speech signal transmission between two low cost Nexys-4 DDR FPGA platforms, operating in real-time for both wired and wireless communications. Compared to similar works, high performances have been obtained in terms of bandwidth efficiency due to the use of DWT, limited area of FPGA resources, low power consumption and high security level with a large keyspace that is sufficient to resist against brute force attacks. The designed system can be a very useful solution for many real-time secure integrated voice communication systems, multiple communication purposes, military, professional or personal high level of conversations security.

Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs

Field-Programmable Gate Arrays (FPGAs), renowned for their high performance per watt, are extensively utilized to accelerate Convolutional Neural Networks (CNNs) in edge computing environments, primarily employing dataflow-based and instruction set-based approaches. Compared to the instruction set-based approach that features fast and versatile circuit design, the dataflow-based approach can significantly enhance performance at the expense of design versatility. Nevertheless, edge computing environments require both high energy efficiency and adaptability to various scenarios. This paper proposes a novel end-to-end heterogeneous acceleration framework for CNN inference on FPGAs, named Pflow. The basic idea is to decouple network deployment and hardware details with a hardware–software co-design approach. First, a dataflow accelerator with an adaptive scheduling strategy is proposed. The adaptive scheduling strategy, along with a scalable design, maximizes hardware utilization in terms of computing resources and bandwidth. Secondly, we design a novel operator-perception method to automate the processes of network reconstruction and operator fusion. Thirdly, we integrate Pflow into the industrial-grade deep learning framework Paddle-Lite. We evaluate Pflow by implementing several networks on two representative FPGA platforms. Experimental results demonstrate that Pflow achieves energy efficiencies of 46.5 GOPS/W on Xilinx Zynq Ultrascale+ MPSoC 3EG and 59.4 GOPS/W on Virtex UltraScale+ XCVU13P. It also reaches a throughput of up to 255.7 GOPS on the former and 3.686 TOPS on the latter.

Acceleration of Graph Neural Network-Based Prediction Models in Chemistry via Co-Design Optimization on Intelligence Processing Units.

Atomic structure prediction and associated property calculations are the bedrock of chemical physics. Since high-fidelity ab initio modeling techniques for computing the structure and properties can be prohibitively expensive, this motivates the development of machine-learning (ML) models that make these predictions more efficiently. Training graph neural networks over large atomistic databases introduces unique computational challenges, such as the need to process millions of small graphs with variable size and support communication patterns that are distinct from learning over large graphs, such as social networks. We demonstrate a novel hardware-software codesign approach to scale up the training of atomistic graph neural networks (GNN) for structure and property prediction. First, to eliminate redundant computation and memory associated with alternative padding techniques and to improve throughput via minimizing communication, we formulate the effective coalescing of the batches of variable-size atomistic graphs as the bin packing problem and introduce a hardware-agnostic algorithm to pack these batches. In addition, we propose hardware-specific optimizations, including a planner and vectorization for the gather-scatter operations targeted for Graphcore's Intelligence Processing Unit (IPU), as well as model-specific optimizations such as merged communication collectives and optimized softplus. Putting these all together, we demonstrate the effectiveness of the proposed codesign approach by providing an implementation of a well-established atomistic GNN on the Graphcore IPUs. We evaluate the training performance on multiple atomistic graph databases with varying degrees of graph counts, sizes, and sparsity. We demonstrate that such a codesign approach can reduce the training time of atomistic GNNs and can improve their performance by up to 1.5× compared to the baseline implementation of the model on the IPUs. Additionally, we compare our IPU implementation with a Nvidia GPU-based implementation and show that our atomistic GNN implementation on the IPUs can run 1.8× faster on average compared to the execution time on the GPUs.

Tailor : Altering Skip Connections for Resource-Efficient Inference

Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and off-chip memory utilization and bandwidth requirements. In this article, we show that skip connections can be optimized for hardware when tackled with a hardware-software codesign approach. We argue that while a network’s skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware-efficient implementation with minimal to no accuracy loss. We introduce Tailor , a codesign tool whose hardware-aware training algorithm gradually removes or shortens a fully trained network’s skip connections to lower the hardware cost. Tailor improves resource utilization by up to 34% for block random access memories (BRAMs), 13% for flip-flops (FFs), and 16% for look-up tables (LUTs) for on-chip, dataflow-style architectures. Tailor increases performance by 30% and reduces memory bandwidth by 45% for a two-dimensional processing element array architecture.

Teaching Edge AI at the Undergraduate Level: A Hardware–Software Co-Design Approach

Teaching Edge AI at the Undergraduate Level: A Hardware–Software Co-Design Approach

Hardware Software Co-Design for Impact Localization using Hybrid Laminates

Impact detection using piezoelectric sensors is an actual and widespread research field. The current work provides an approach for a real-time realization of an impact detection system using deep learning methods. For realization a hardware software co-design approach is used utilizing hardware acceleration by a continuous pipelining FPGA structure. The concept describes the hardware software partitioning of the underlying functions and the methodology for ensuring continuous data processing and the associated real-time capability. The behavior of the hardware is realized with the help of a finite state machine and thus the correctness of the data is ensured and the impact identification is realized. The results show the real-time capability as well as a reasonable resource utilization of the FPGA design.

An Integrated Off-Line Echo Signal Acquisition System Implemented in SoC-FPGA for High Repetition Rate Lidar

High repetition rate lidar is typically equipped with a low-energy, high repetition rate laser, and small aperture telescopes. Therefore, it is small, compact, low-cost, and can be networked for observation. However, its data acquisition and control functions are generally not specially designed, and the data acquisition, storage, and control programs need to be implemented on an IPC (Industrial Personal Computer), which increases the complexity and instability of the lidar system. Therefore, this paper designs an integrated off-line echo signal acquisition system (IOESAS) for lidar developed based on SoC FPGA (System-On-Chip Field Programmable Gate Array). Using a hardware–software co-design approach, the system is implemented in a heterogeneous multi-core chip ZYNQ-7020 (integrated FPGA and ARM). The FPGA implements dual-channel echo data acquisition (gated counting and hardware accumulation). At the same time, the ARM performs laser control and monitoring, laser pointing control, pulse energy monitoring, data storage, and wireless transmission. Offline data acquisition and control software was developed based on LabVIEW, which can remotely control the status of the lidar and download the echo data stored in IOESAS. To verify the performance of the data acquisition system, IOESAS was compared with the photon counting card P7882 and MCS-PCI, respectively. The test results show that they are in good agreement; the linear correlation coefficients were 0.99967 and 0.99884, respectively. IOESAS was installed on lidar outdoors for continuous detection, and the system was able to work independently and stably in different weather conditions, and control functions were tested normally. The gating delay and gating width time jitter error are ±5 ns and ±2 ns, respectively. The IOESAS is now used in several small lidars for networked observations.

Adaptive Real-Time Object Detection for Autonomous Driving Systems.

Accurate and reliable detection is one of the main tasks of Autonomous Driving Systems (ADS). While detecting the obstacles on the road during various environmental circumstances add to the reliability of ADS, it results in more intensive computations and more complicated systems. The stringent real-time requirements of ADS, resource constraints, and energy efficiency considerations add to the design complications. This work presents an adaptive system that detects pedestrians and vehicles in different lighting conditions on the road. We take a hardware-software co-design approach on Zynq UltraScale+ MPSoC and develop a dynamically reconfigurable ADS that employs hardware accelerators for pedestrian and vehicle detection and adapts its detection method to the environment lighting conditions. The results show that the system maintains real-time performance and achieves adaptability with minimal resource overhead.

RETRACTED ARTICLE: Computer development based embedded systems in precision agriculture: tools and application

This article has been retracted from publication in the Taylor & Francis journal, Acta Agriculturae Scandinavica, Section B — Soil & Plant Science. Following publication, concerns were raised by multiple third-parties around the content of the special issue and the decision-making process. Following an investigation by the Taylor & Francis Publishing Ethics & Integrity team in full cooperation with the Editor-in-Chief, it was confirmed that this article included in Special Issue titled “ Envisage Computer Modelling and Statistics for Agriculture”, guest edited by Gunasekaran Manogaran was not peer-reviewed appropriately, in line with the Journal's peer review standards and policy. As the stringency of the peer review process is core to the integrity of the publication process, the Editor and Publisher have decided to retract all of the articles within the above-named Special Issue. The journal has not confirmed if the authors were aware of this compromised peer review process. The journal is committed to correcting the scientific record and will fully cooperate with any institutional investigations into this matter. The authors have been informed of this decision. We have been informed in our decision-making by our policy on publishing ethics and integrity and the COPE guidelines.

AXI-IC^{RT}: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs

In modern real-time heterogeneous System-on-Chips (SoCs), ensuring the predictability of interconnects is becoming increasingly important. Most of the existing interconnects are mainly designed to achieve high throughput, with their micro-architectures usually based on FIFO queues. The FIFO-based design prevents transaction prioritization based on importance and leads to occurrences of physical priority inversion. Such problems lead to difficulties in ensuring transaction predictability, especially when the system scales to a large number of elements. In this paper, we introduce AXI-Interconnect^{rt} (AXI-IC^{rt}, for short) -- a real-time AXI interconnect for heterogeneous SoCs, which redefines the micro-architecture of interconnects by enabling random accesses of buffered transactions and organizing transactions through compositional scheduling. This hardware-software co-design approach provides predictable and scalable real-time performance for highly integrated SoCs.

Emerging GaN technologies for power, RF, digital, and quantum computing applications: Recent advances and prospects

GaN technology is not only gaining traction in power and RF electronics but is also rapidly expanding into other application areas including digital and quantum computing electronics. This paper provides a glimpse of future GaN device technologies and advanced modeling approaches that can push the boundaries of these applications in terms of performance and reliability. While GaN power devices have recently been commercialized in the 15–900 V classes, new GaN devices are greatly desirable to explore both higher-voltage and ultra-low-voltage power applications. Moving into the RF domain, ultra-high frequency GaN devices are being used to implement digitized power amplifier circuits, and further advances using the hardware–software co-design approach can be expected. On the horizon is the GaN CMOS technology, a key missing piece to realize the full-GaN platform with integrated digital, power, and RF electronics technologies. Although currently a challenge, high-performance p-type GaN technology will be crucial to realize high-performance GaN CMOS circuits. Due to its excellent transport characteristics and ability to generate free carriers via polarization doping, GaN is expected to be an important technology for ultra-low temperature and quantum computing electronics. Finally, given the increasing cost of hardware prototyping of new devices and circuits, the use of high-fidelity device models and data-driven modeling approaches for technology-circuit co-design are projected to be the trends of the future. In this regard, physically inspired, mathematically robust, less computationally taxing, and predictive modeling approaches are indispensable. With all these and future efforts, we envision GaN to become the next Si for electronics.

An FSCV Deep Neural Network: Development, Pruning, and Acceleration on an FPGA.

Fast-scan cyclic voltammetry (FSCV) is an electrochemical technique for measuring rapid changes in the extracellular concentration of neurotransmitters within the brain. Due to its fast scan rate and large output-data size, the current analysis of the FSCV data is often conducted on a computer external to the FSCV device. Moreover, the analysis is semi-automated and requires a good understanding of the characteristics of the underlying chemistry to interpret, making it unsuitable for real-time implementation on low-resource FSCV devices. This paper presents a hardware-software co-design approach for the analysis of FSCV data. Firstly, a deep neural network (DNN) is developed to predict the concentration of a dopamine solution and identify the data recording electrode. Secondly, the DNN is pruned to decrease its computation complexity, and a custom overlay is developed to implement the pruned DNN on a low-resource FPGA-based platform. The pruned DNN attains a recognition accuracy of 97.2% with a compression ratio of 3.18. When the DNN overlay is implemented on a PYNQ-Z2 platform, it achieves the execution time of 13 ms and power consumption of 1.479 W on the entire PYNQ-Z2 board. This study demonstrates the possibility of operating the DNN for FSCV data analysis on portable FPGA-based platforms.

Three-Dimensional Neuromorphic Computing System With Two-Layer and Low-Variation Memristive Synapses

Three-dimensional Integrated Circuits (3D-ICs) is a cutting-edge design methodology of placing the circuitry vertically aiming for a high-speed and energy-efficient system with the smallest design area. In this paper, a novel 3D neuromorphic system is proposed and analyzed, which utilizes the fabricated two-layer memristor as the electronic synapses in a spiking neural network (SNN). The two-layer structure of the memristors leads to a significant improvement in the design area (2×), power consumption (1.48 ×), and latency (2.58×), compared to the traditional one-layer configuration. Meanwhile, the heat dissipation layers are added to our memristors reducing 30% cycle-to-cycle switching variation. Our memristive synapses are utilized for storing the exported weights of the SNNs that have threshold function as the activation function. The proposed neuromorphic system is evaluated using a hardware-software co-design approach importing the weights of SNNs into NeuroSIM. The simulation results demonstrate the significant improvement of memristive synapses on design area, power consumption, and latency, compared with the SRAM (Static Random-access Memory) and other state-of-the-art memristive synapses (10% to 66%).

Real-time FPGA implementation of a secure chaos-based digital crypto-watermarking system in the DWT domain using co-design approach

In this paper a new approach for designing invisible non-blind full crypto-watermarking system targeting images security on FPGA platform is presented. This new design is based on the Hardware-Software co-design approach using the High-Level Synthesis (HLS) tool of Xilinx which allows a good compromise between development time and performances. For a better authentication and robustness of the proposed system, the Discrete Wavelet Transform (DWT) is employed. To more enhance the security level, a new chaos-based generator proposed is integrated into a stream cipher algorithm in order to encrypt and decrypt the watermark during the insertion and extraction phases.This approach allows a better secure access at the positions of the watermark and to distribute the watermark evenly throughout the image. Three novel customized Intellectual Property (IP) cores designed under HLS tool, implementing Haar DWT and the new chaos-based key generator, have been generated, tested, and validated. The generated Register Transfer Level-IP (RTL-IP) cores are integrated into a Vivado library that achieves real-time secured watermarking operations for both embedding and extraction processes. The system has been evaluated using the main metrics in terms of imperceptibility of the produced watermarked images achieving a Peak Signal to Noise Ratio (PSNR) of 47 dB, robustness against most geometric and image processing attacks achieving a Normalized Cross-Correlation (NCC) of 0.99. The proposed crypt-watermarking system allows a good solution against brute force attack which produce a huge key-space of $$2^{768}$$ . Finally, the implementation offers a good efficiency value of 0.19 MHz/LUT in terms of FPGA resource consumption and speed, making the system a reliable choice for real sensitive embedded applications.

Toward Intelligent Reconfigurable Wireless Physical Layer (PHY)

Next-generation wireless networks are getting significant attention because they promise 10-factor enhancement in mobile broadband along with the potential to enable new heterogeneous services. Services include massive machine type communications desired for Industrial 4.0 along with ultra-reliable low latency services for remote healthcare and vehicular communications. In this article, we present the design of intelligent and reconfigurable physical layer (PHY) to bring these services to reality. First, we design and implement the reconfigurable PHY via a hardware-software co-design approach on system-on-chip consisting of the ARM processor and field-programmable gate array (FPGA). The reconfigurable PHY is then made intelligent by augmenting it with online machine learning (OML) based decision-making algorithm. Such PHY can learn the environment (for example, wireless channel) and dynamically adapt the transceivers' configuration (i.e., modulation scheme, word-length) and select the wireless channel on-the-fly. Since the environment is unknown and changes with time, we make the OML architecture reconfigurable to enable dynamic switch between various OML algorithms on-the-fly. We have demonstrated the functional correctness of the proposed architecture for different environments and word-lengths. The detailed throughput, latency, and complexity analysis validate the feasibility and importance of the proposed intelligent and reconfigurable PHY in next-generation networks.

Spectral Coexistence of LDACS and DME: Analysis via Hardware Software Co-Design in Presence of Real Channels and RF Impairments

To meet the exponentially increasing air traffic, L-band (960--1164 MHz) digital aeronautical communication system (LDACS) has been introduced. The LDACS aims to exploit the vacant spectrum between incumbent Distance Measuring Equipment (DME) signals and envisioned to follow an orthogonal frequency division multiplexing (OFDM) approach to support high-speed delay-sensitive multimedia services. This paper deals with the design and implementation of end-to-end LDACS the transceiver on the Zynq System on Chip platform, consisting of FPGA as programmable logic (PL) and ARM as processing system (PS). We consider OFDM based LDACS and improve it further using windowing and/or filtering. We propose a hardware-software co-design approach and analyze various transceiver configurations by dividing it into PL and PS. We demonstrate the flexibility offered by such a co-design approach to choose the configuration as well as word-length for a given area, delay and power constraints. The transceiver is also integrated with the programmable analog front-end to validate its functionality in the presence of various RF impairments and wireless channels and interference specific to the LDACS environment. Via in-depth performance analysis concerning parameters such as out-of-band attenuation, DME interference, bit-error-rate, word-length, and complexity, we demonstrate wide bandwidth filtered OFDM as an attractive solution for the next generation LDACS.

Labeled Network Stack: A High-Concurrency and Low-Tail Latency Cloud Server Framework for Massive IoT Devices

Internet of Things (IoT) applications have massive client connections to cloud servers, and the number of networked IoT devices is remarkably increasing. IoT services require both low-tail latency and high concurrency in datacenters. This study aims to determine whether an order of magnitude improvement is possible in tail latency and concurrency in mainstream systems by proposing a hardware–software codesigned labeled network stack (LNS) for future datacenters. The key innovation is a cross-layered payload labeling mechanism that distinguishes different requests by payload across the full network stack, including application, TCP/IP, and Ethernet layers. This type of design enables prioritized data packet processing and forwarding along the full datapath, such that latency-insensitive requests cannot significantly interfere with high-priority requests. We build a prototype datacenter server to evaluate the LNS design against a commercial X86 server and the mTCP research, using a cloud-supported IoT application scenario. Experimental results show that the LNS design can provide an order of magnitude improvement in tail latency and concurrency. A single datacenter server node can support over 2 million concurrent long-living connections for IoT devices as a 99-percentile tail latency of 50 ms is maintained. In addition, the hardware–software codesign approach remarkably reduces the labeling and prioritization overhead and constrains the interference of high-priority requests to low-priority requests.

Hardware Acceleration of SVM classifier using Zynq SoC FPGA

Support Vector Machines (SVM) is one of the most commonly used the state-of-the-art supervised machine learning algorithm for various classification problems. It provides high accuracy rate compared to other classification algorithms. However, When SVM is modelled only using Software, it is a time consuming algorithm due to its high computational complexity. This makes the algorithm to be not suitable for embedded real time applications. We propose a new hardware software co-design approach to achieve the real time performance by accelerating the computationally intensive classifier part of the algorithm as a custom hardware Intellectual Property (IP) core. In this paper, a novel Support Vector Machine (SVM) linear classifier is modelled as a custom hardware Intellectual Property (IP) core using High Level Synthesis (HLS). The developed IP core is optimized for latency and hardware resource utilization by applying various directives of HLS tool. The synthesis results of the IP core for Skin segmentation dataset is reported. The proposed hardware software co-design approach is implemented in real time on Zynq-7000 XC7Z020 System on Chip (SoC) field programmable gate arrays (FPGA). A detailed comparative results of proposed hardware software co-design approach and the complete software approach is reported in this work for Iris and Breast cancer dataset. A promising result of 18x speedup is achieved using SVM classifier hardware IP compared to is software counterpart.

Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms

This paper presents a performance comparison of new authenticated encryption (AE) algorithms which are aimed at providing better security and resource efficiency compared to existing standards. Specifically, these algorithms improve the security of existing AE standards by providing a critical property termed nonce-misuse resistance. This paper addresses algorithm to architectural mappings of several candidates from the ongoing Competition for AE: Security, Applicability, and Robustness as well as a submission from the Crypto Forum Research Group. Implementations of the architectures on both field-programmable gate arrays and application-specific integrated circuits platforms are provided and compared with the architecture of a popular standard: Advanced Encryption Standard in Galois Counter mode (AES-GCM). Optimizations that are applicable to AE, in general, and nonce-misuse-resistant architectures, in particular, are presented. A hardware–software codesign approach to optimization is also discussed. The implementations via proposed optimizations demonstrate that new AE algorithms can provide comparable performance as standard AES-GCM while enhancing security and resource utilization for specific use-case scenarios.

Design of PTP TC/Slave Over Seamless Redundancy Network for Power Utility Automation

IEC 61850, which drives to digitalize information in the entire system, is being increasingly adopted in the power utility industry, since the last decade. It is necessary for all devices communicating with distributed digital data to have a common understanding of time. As protection and control devices are directly related to the safety of the power system, they are strictly required to have time accuracies. This paper describes the design of a hybrid slave clock with the transparent clock (TC) functionality defined in the IEEE 1588 precision time protocol. The design objective includes not only the synchronization of the time accuracy but also the transient time, as specified in the IEC/IEEE 61850-9-3 precision time profile for power utility automation. To comply with these objectives, we adopt a hardware–software co-design approach. The timestamp of each port is implemented by hardware. Also, they are connected by hardware to calculate the bridge time on the fly, enabling the design to have a one-step TC functionality with low latency. On the other hand, the synchronizing controller is implemented by software for adapting to the varying external conditions. The controller uses the linear quadratic Gaussian (LQG) to achieve stable steady-state performance. Simultaneously, the least-squares estimator is utilized to estimate the initial conditions of the LQG controller for reducing the transition time. Experimental results show the three-sigma time inaccuracies are 15.6 ns for the TC and 149 ns for the slave with an average transition time of 13.5 s, satisfying the IEEE/IEC 61850-9-3 criteria.