Hardware Power Consumption Research Articles

A runtime-reconfigurable convolutional engine using tensor multiplication with multiple computing modes in 22-nm CMOS

The ultra-low power consumption and flexible configurability of hardware are urgent for resource-constrained artificial intelligence of things (AIoT). Thus, we propose a convolutional engine using tensor multiplication. It consists of a reconfigurable processing element (RPE) array to dynamically adjust convolutional operations with varying kernel sizes during runtime. Implemented in a 22-nm CMOS process, the proposed RPE cluster achieves high energy efficiency, flexibility, and resource utilization with low-cost hardware overhead as compared to state-of-the-art (SOTA) PE architectures. Furthermore, multiply-accumulate (MAC) operations in RPE support accurate and multiple approximate computing modes. Approximate modes achieve a configurable approximation degree, coupled with a search strategy for the approximation factor to improve energy efficiency. In the neural network-based keyword spotting (KWS) task, RPE cluster with the proposed approximation solution saves the whole system's power consumption by 34.64 % with only 0.7 % accuracy loss as compared to using accurate computing modes altogether. It achieves the lowest inference energy as compared to the SOTA.

Hardware Design and Implementation of a Lightweight Saber Algorithm Based on DRC Method

With the development of quantum computers, the security of classical cryptosystems is seriously threatened, and the Saber algorithm has become one of the potential candidates for post-quantum cryptosystems (PQCs). To address the problems of long delay and the high power consumption of Saber algorithm hardware implementation, a lightweight Saber algorithm hardware design scheme based on the joint optimization of data readout and clock (DRC) was proposed. Firstly, an analysis was carried out on the hardware architecture, timing overhead and power consumption distribution of the Saber algorithm, and the key circuits that limit the performance of the algorithm were identified; secondly, a dual-port SRAM parallel reading method was adopted to improve the data reading efficiency and reduce the timing overhead of double data reading in the multiplier module. Then, a clock gating technology was used to reduce the dynamic flipping probability of internal registers and reduce the hardware power consumption of the Saber algorithm; finally, data reading and clock gating were jointly optimized to design a high-speed and low-power Saber algorithm hardware IP core. Lightweight IP cores were integrated into RISC-V SoC systems via APB bus in a TSMC 65 nm process to complete the digital back-end design. The experimental results show an IP core area of 0.99 mm2 and power consumption of 8.49 mW, which is 33% lower than that reported in the related literature. Under 72 MHz & 1 V operating conditions, the number of clock cycles for the Saber algorithm’s key generation, encryption and decryption are 3315, 9204 and 1420, respectively.

Escope: An Energy Efficiency Simulator for Internet Data Centers

Contemporary megawatt-scale data centers have emerged to meet the increasing demand for online cloud services and big data analytics. However, in such large-scale data centers, servers of different generations are installed gradually year by year, making the data center heterogeneous in computing capability and energy efficiency. Furthermore, due to different processor architectures, complex and diverse load dynamic changing, business coupling, and other reasons, operators pay great attention to processor hardware power consumption and server aggregation energy efficiency. Therefore, the simulation and analysis of the energy efficiency characteristics of data center servers under different processor architectures can help operators understand the energy efficiency characteristics of data centers and make the optimal task scheduling strategy. This is very beneficial for improving the energy efficiency of the production system and the entire data center. The Escope simulator designed in this study can simulate the online quantity (placement strategy) of different types of servers in the data center and the optimal operating range of the servers. The purpose of this is to analyze the energy efficiency characteristics of all servers in the data center and provide data center operators with the energy efficiency and energy proportionality characteristics of different servers, improve server utilization, and perform reasonable scheduling. Through the simulation experiment of Escope, it can be proved that running the server at the highest energy efficiency point or running the server under full load cannot improve the energy efficiency of the entire data center. The simulation algorithm provided by Escope can select the optimal set of servers and their corresponding utilization. Escope can set up a variety of simulation strategies, and data center operators can simulate data center energy efficiency according to their own needs. Escope can also calculate the power cost savings of introducing new servers in the data center, which provides an essential reference for operators to purchase servers and design data centers.

A review of cryogenic neuromorphic hardware

The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here, we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insight to circumvent these challenges for the future progression of research.

ECG Classification Using an Optimal Temporal Convolutional Network for Remote Health Monitoring.

Increased life expectancy in most countries is a result of continuous improvements at all levels, starting from medicine and public health services, environmental and personal hygiene to the use of the most advanced technologies by healthcare providers. Despite these significant improvements, especially at the technological level in the last few decades, the overall access to healthcare services and medical facilities worldwide is not equally distributed. Indeed, the end beneficiary of these most advanced healthcare services and technologies on a daily basis are mostly residents of big cities, whereas the residents of rural areas, even in developed countries, have major difficulties accessing even basic medical services. This may lead to huge deficiencies in timely medical advice and assistance and may even cause death in some cases. Remote healthcare is considered a serious candidate for facilitating access to health services for all; thus, by using the most advanced technologies, providing at the same time high quality diagnosis and ease of implementation and use. ECG analysis and related cardiac diagnosis techniques are the basic healthcare methods providing rapid insights in potential health issues through simple visualization and interpretation by clinicians or by automatic detection of potential cardiac anomalies. In this paper, we propose a novel machine learning (ML) architecture for the ECG classification regarding five heart diseases based on temporal convolution networks (TCN). The proposed design, which implements a dilated causal one-dimensional convolution on the input heartbeat signals, seems to be outperforming all existing ML methods with an accuracy of 96.12% and an F1 score of 84.13%, using a reduced number of parameters (10.2 K). Such results make the proposed TCN architecture a good candidate for low power consumption hardware platforms, and thus its potential use in low cost embedded devices for remote health monitoring.

Secure spatial modulation based on two-dimensional generalized weighted fractional Fourier transform encryption

In this paper, a two-dimensional generalized weighted fractional Fourier transform (2DGWFRFT) and constellation scrambling (CS)-based secure spatial modulation (SM) scheme, called 2DGWFRFT-CS-SM, is proposed to enhance the physical layer security (PLS) of the wireless communication system. The proposed scheme is executed by two steps. In the first step, 2DGWFRFT is implemented as the security kernel for PLS provision. In the second step, the parameters of 2DGWFRFT, regarded as the encryption core, control the antenna number rotation to further enhance the security of the SM modulation symbol. Both the 2DGWFRFT signal generation strategy and the SM system including the transfer process have been elaborated to depict the security mechanism of the proposed scheme. Moreover, we give a key extraction algorithm utilized to generate the parameters, which can help scramble the antenna serial number. From the perspective of signal characteristics, the uniqueness of variation in the constellation has been investigated to outperform other cryptography-based encryption algorithms. Finally, the secrecy rates and the energy efficiency of our proposed scheme are theoretically analyzed and evaluated via Monte Carlo simulations, demonstrating that the proposed scheme can achieve a much higher secrecy capacity than artificial noise schemes without requiring additional jamming power consumption and myriad costs of hardware.

YOLOv4-Tiny-Based Coal Gangue Image Recognition and FPGA Implementation.

Nowadays, most of the deep learning coal gangue identification methods need to be performed on high-performance CPU or GPU hardware devices, which are inconvenient to use in complex underground coal mine environments due to their high power consumption, huge size, and significant heat generation. Aiming to resolve these problems, this paper proposes a coal gangue identification method based on YOLOv4-tiny and deploys it on the low-power hardware platform FPGA. First, the YOLOv4-tiny model is well trained on the computer platform, and the computation of the model is reduced through the 16-bit fixed-point quantization and the integration of a BN layer and convolution layer. Second, convolution and pooling IP kernels are designed on the FPGA platform to accelerate the computation of convolution and pooling, in which three optimization methods, including input and output channel parallelism, pipeline, and ping-pong operation, are used. Finally, the FPGA hardware system design of the whole algorithm is completed. The experimental results of the self-made coal gangue data set indicate that the precision of the algorithm proposed in this paper for coal gangue recognition on the FPGA platform are slightly lower than those of CPU and GPU, and the mAP value is 96.56%; the recognition speed of each image is 0.376 s, which is between those of CPU and GPU; the hardware power consumption of the FPGA platform is only 2.86 W; and the energy efficiency ratio is 10.42 and 3.47 times that of CPU and GPU, respectively.

SoC Root Canal!

Finding the root cause of power-based side-channel leakage becomes harder when multiple layers of design abstraction are involved. While side-channel leakage originates in processor hardware, the dangerous consequences may only become apparent in the cryptographic software that runs on the processor. This contribution presents RootCanal, a methodology to explain the origin of side-channel leakage in a software program in terms of the underlying micro-architecture and system architecture. We simulate the hardware power consumption at the gate level and perform a non-specific test to identify the logic gates that contribute most sidechannel leakage. Then, we back-annotate those findings to the related activities in the software. The resulting analysis can automatically point out non-trivial causes of side-channel leakages. To illustrate RootCanal’s capabilities, we discuss a collection of case studies.

Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver

In 4G turbo and 5G LDPC, in order to realize a flexible, low-power, low-cost shared general-purpose block interleaving hardware module, it faces the challenges of interleaving structure integration, fewer gate circuits, parallel multistream operation, and switching between standards. Facing these challenges, after studying 3GPP TS 36.212 V15.4.0 and 3GPP TS 38.212 V15.4.0 protocols, common part of two major interleaving module standards is found. For the block interleave module in the rate matching of the 4G downlink turbo code and the bit interleave module after the rate matching of the 5G NR downlink LDPC code, this paper first designs a memory and implements the two codes interleaving on it. Then, based on the Altera Quartus prime platform and ModelSim for functional verification. Experimental results show that under SMIC 28 nm, operating frequency 50MHz, after synopsys synthesis, the memory module area is 0.17 μ m 2 , and the power consumption is 6.45 mW. Through the shared design, 32 bits parallel access, and switching between standards, the proposed scheme reduces the hardware cost, power consumption, and clock overhead, and improves the flexibility of 4G LTE and 5G NR communication downlink hardware implementation.

The enhanced beam sweeping algorithm for DOA estimation in the hybrid analog-digital structure with nested array

As an emerging technology, the hybrid analog-digital structure has been considered for use in future millimeter-wave communications. Although this structure can reduce the hardware cost and power consumption considerably, the spatial covariance matrix (SCM), as the core of subspace-based direction of arrival (DOA) estimation, cannot be obtained directly. Previously, the beam sweeping algorithm (BSA) has been found effective for reconstructing the spatial covariance matrix and realizing DOA estimation by forming the beams to difference directions. However, it is computationally intractable owing to the high-dimensional matrix operation. To address this problem and improve the DOA estimation performance, this paper applies the nested array to the hybrid analog-digital structure and proposes the enhanced BSA (EBSA) for DOA estimation. By deleting a large number of redundant elements exist in the SCM to be reconstructed, the computational cost can be considerably reduced. Also, the nested array can offer high degrees of freedom. Finally, simulation experiments are conducted to verify the performance of EBSA. The results indicate that the proposed EBSA is better than the state-of-the-art method in terms of estimation accuracy and computational cost.

Research on Indoor Positioning Algorithm Based on SAGA-BP Neural Network

The Indoor positioning based on the ZigBee received signal strength index has attracted more and more researchers’ attention and, due to its low cost, low hardware power consumption and easy implementation. However, because of multipath effects and shadow effects, traditional indoor positioning algorithms cannot obtain good positioning effects. In order to improve the accuracy of ZigBee indoor positioning, this paper proposes an indoor positioning algorithm of annealing algorithm (SA) and genetic algorithm (GA) optimized neural network (SAGA-BP), and the superiority of this algorithm is proved through simulation and experiment. First, establish the position relationship between the received signal strength indicator(RSSI) and the target position, and arrange the node network structure model to collect signals to establish a fingerprint database. Then use the mechanism of the annealing algorithm combined with the genetic algorithm to optimize the initial weight and initial threshold of the neural network algorithm, so that it can quickly jump out of the local optimal solution and achieve high-precision positioning. Experiments have proved the effectiveness of the positioning algorithm. Compared with BP and GA-BP algorithms, SAGA-BP positioning algorithm has an average error of 0.75m for RSSI signals after acquisition and processing, and an average error of BP positioning algorithm is 1.24m. The average error of GA-BP algorithm is 0.98m. Thus, the SAGA-BP algorithm has higher positioning accuracy.

Efficient, Geometry-Based Convolution

Several computationally intensive applications in machine learning, signal processing, and computer vision call for convolution between a fixed vector and each of the incoming vectors. Often, the convolution need not be exact because a subsequent processing unit, such as an activation function in a neuron network or a visual unit in image processing, can tolerate a computational error, hence allowing the optimization of the convolution algorithm. This paper develops a method of approximate convolution and quantifies its performance in software and hardware. The key idea is to take advantage of the known fixed vector, view a convolution as a dot product, and approximate the angles between the fixed vector and an incoming vector geometrically. We evaluate the proposed method in terms of the accuracy, running time complexity, and hardware power consumption on the field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware platforms. In a benchmark test, the accuracy of the approximate convolution is 3.7% lower than that of the exact convolution, a tolerable loss for machine learning and signal processing. The proposed method reduces the number of operations in the hardware, and reduces the power consumption of conventional convolution by approximately 20% and the existing approximate convolution by approximately 10%, while maintaining the same throughput and latency. We also test the proposed method on 2D convolution and convolutional neural network (CNN). The proposed method reduces complexity, power consumption for 2D convolution, and power consumption for CNN of the conventional method by approximately 22%, 25%, and 13%, respectively. The proposed method of approximate convolution trades off accuracy with running time complexity and hardware power consumption, and it has practical utility in computationally intensive tasks that tolerate a margin of convolutional error.

Adaptive Moving Ground-Target Detection Method Based on Seismic Signal

Moving ground-target detection system is widely used to monitor illegal activities of pedestrians and vehicles. However, existing detection methods are restricted by the power consumption in hardware and are usually based on some single feature of the seismic signal, which leads to low detection accuracy and false alarms. To address these issues, we propose a new moving ground-target detection method for detecting the weak seismic signals generated by distant moving ground targets. This method combines an adaptive strategy and support vector machines (SVMs). Both time- and frequency-domain features of seismic signals are considered in the detection method. Additionally, we carry out field experiments to evaluate the performance of the proposed method. The results show that the proposed moving ground-target detection method can detect distant moving ground targets and avoid false alarms as many as possible, which indicates good performance.

Efficient Security Architecture for Physical Layer in mmWave Communication Systems

Employing mmWave is a good way to achieve the data demands for the new and future generations of communication systems. In order to decrease power consumption and complexity of hardware, hybrid precoding is implemented for mmWave systems with large scale antenna. Lack of secure communication paths in mmWave multiple-input multiple-output (MIMO) systems leads to attack and degrade the system efficiency. For secure communications, this paper proposes a deep and secure hybrid precoder and decoder design for mmWave MIMO systems to maximize the secrecy rate. Lack of secure communication paths being eavesdropped by Eves is illustrated and the scatterer sharing channel model is assumed. The proposed algorithm consists of two convolutional neural networks for calculating the secure RF analog precoder, and then obtains the digital precoder that can further improve the security. In addition, singular value decomposition technique based physical layer security is implemented to determine digital precoders. Results showed that the secrecy performance improvement of the proposed algorithm in comparison to the benchmark algorithms and algorithms based on optimization methods.

The Design of Home Fire Monitoring System based on NB-IoT

In the field of home fire monitoring, the currently relatively mature monitoring solutions include GPRS/GSM com-munication and Zigbee communication. The main disadvantage of GPRS wireless communication is high power consumption, and the disadvantage of Zigbee technology is that it needs to be combined with other communication technologies to realize remote monitoring. In addition, the above technical solutions all require self-built local or remote monitoring servers to save mon-itoring data. In view of the above problems, this system designs a home fire monitoring system based on NB-IoT technology and cloud platform. The system uses a single-chip STM32F103C8T6 as the core controller and contains a sensor data acquisition module and a narrowband IoT communication module. The data fusion of multi-sensor data is performed by BP neural network algorithm.On the basis of remote transmission, the system solves the problems of high power consumption, high cost and insufficient signal coverage of terminal hardware. The system can collect indoor environmental parameters and fire information in real time, and upload them to the cloud platform for storage. If abnormal data is detected, an early warning message will be issued. The feasibility of the system is verified, and the verification results show that the system works normally and the output is accurate, which meets the design requirements and can be widely used.

Hardware-Based Activation Function-Core for Neural Network Implementations

Today, embedded systems (ES) tend towards miniaturization and the carrying out of complex tasks in applications such as the Internet of Things, medical systems, telecommunications, among others. Currently, ES structures based on artificial intelligence using hardware neural networks (HNNs) are becoming more common. In the design of HNN, the activation function (AF) requires special attention due to its impact on the HNN performance. Therefore, implementing activation functions (AFs) with good performance, low power consumption, and reduced hardware resources is critical for HNNs. In light of this, this paper presents a hardware-based activation function-core (AFC) to implement an HNN. In addition, this work shows a design framework for the AFC that applies a piecewise polynomial approximation (PPA) technique. The designed AFC has a reconfigurable architecture with a wordlength-efficient decoder, i.e., reduced hardware resources are used to satisfy the desired accuracy. Experimental results show a better performance of the proposed AFC in terms of hardware resources and power consumption when it is compared with state of the art implementations. Finally, two case studies were implemented to corroborate the AFC performance in widely used ANN applications.

Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

This paper presents a novel spiking neural network (SNN) classifier architecture for enabling always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual wake-up, in ultra-low-power internet-of-things (IoT) devices. Such always-on hardware tends to dominate the power efficiency of an IoT device and therefore it is paramount to minimize its power dissipation. A key observation is that the input signal to always-on hardware is typically sparse in time. This is a great opportunity that a SNN classifier can leverage because the switching activity and the power consumption of SNN hardware can scale with spike rate. To leverage this scalability, the proposed SNN classifier architecture employs event-driven architecture, especially fine-grained clock generation and gating and fine-grained power gating, to obtain very low static power dissipation. The prototype is fabricated in 65 nm CMOS and occupies an area of 1.99 mm2. At 0.52 V supply voltage, it consumes 75 nW at no input activity and less than 300 nW at 100% input activity. It still maintains competitive inference accuracy for KWS and other always-on classification workloads. The prototype achieved a power consumption reduction of over three orders of magnitude compared to the state-of-the-art for SNN hardware and of about 2.3X compared to the state-of-the-art KWS hardware.

A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

Binarized Encoder-Decoder Network and Binarized Deconvolution Engine for Semantic Segmentation

Recently, semantic segmentation based on deep neural network (DNN) has attracted attention as it exhibits high accuracy, and many studies have been conducted on this. However, DNN-based segmentation studies focused mainly on improving accuracy, thus greatly increasing the computational demand and memory footprint of the segmentation network. For this reason, the segmentation network requires a lot of hardware resources and power consumption, and it is difficult to be applied to an environment where they are limited, such as an embedded system. In this paper, we propose a binarized encoder-decoder network ( BEDN ) and a binarized deconvolution engine ( BiDE ) accelerating the network to realize low-power, real-time semantic segmentation. BiDE implements a binarized segmentation network with custom hardware, greatly reducing the hardware resource usage and greatly increasing the throughput of network implementation. The deconvolution used for upsampling in a segmentation network includes zero padding. In order to enable deconvolution in a binarized segmentation network that cannot express zero, we introduce zero-aware binarized deconvolution which skips padded zero activations and zero-aware batch normalization embedded binary activation considering zero-skipped convolution. The BEDN , which is a binarized segmentation network proposed to be accelerated on BiDE , has acceptable accuracy while greatly reducing the computational and memory demands of the segmentation network through full-binarization and simple structure. BEDN has a network size of 0.21 MB, and its maximum memory usage is 1.38 MB. BiDE was implemented on Xilinx ZU7EV field-programmable gate array (FPGA) to operate at 187.5 MHz. BiDE accelerated the proposed BEDN within CamVid11 images of $480\times {360}$ size at 25.89 frames per second (FPS) achieving a performance of 1.682 Tera operations per second (TOPS) and 824 Giga operations per second per watt (GOPS/W).

Development of Wireless Sensor Device for Machine English Oral Pronunciation Noise Detection

There is often noise in spoken machine English, which affects the accuracy of pronunciation. Therefore, how to accurately detect the noise in machine English spoken language and give standard spoken pronunciation is very important and meaningful. The traditional machine‐oriented spoken English speech noise detection technology is limited to the improvement of software algorithm, mainly including speech enhancement technology and speech endpoint detection technology. Based on this, this paper will develop a wireless sensor network based on machine English oral pronunciation noise based on air and nonair conduction, reasonably design and configure air sensors, and nonair conduction sensors to deal with machine English oral pronunciation noise, so as to improve the naturalness and intelligibility of machine English speech. At the hardware level, this paper mainly optimizes the AD sampling, sensor matching layout, and internal hardware circuit board layout of the two types of sensors, so as to solve the compatibility problem between them and further reduce the hardware power consumption. In order to further verify or evaluate the performance of the machine spoken English speech noise detection sensor designed in this paper, a machine spoken English training system based on Android platform is designed. Compared with the traditional system, the training system can improve the intelligence of machine oriented oral English noise detection algorithm, so as to continuously improve the accuracy of system detection. The machine English pronunciation is adjusted and corrected by combining the data sensed by the sensor, so as to form a closed‐loop design. The experimental results show that the wireless sensor sample proposed in this paper has obvious advantages in detecting the accuracy of machine English oral pronunciation, and its good closed‐loop system is helpful to further improve the accuracy of machine English oral pronunciation.