Hardware-oriented Algorithm Research Articles

A Parallel Algorithm for Dividing Octonions

The article presents a parallel hardware-oriented algorithm designed to speed up the division of two octonions. The advantage of the proposed algorithm is that the number of real multiplications is halved as compared to the naive method for implementing this operation. In the synthesis of the discussed algorithm, the matrix representation of this operation was used, which allows us to present the division of octonions by means of a vector–matrix product. Taking into account a specific structure of the matrix multiplicand allows for reducing the number of real multiplications necessary for the execution of the octonion division procedure.

Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions.

Nowadays, computer vision relies heavily on convolutional neural networks (CNNs) to perform complex and accurate tasks. Among them, super-resolution CNNs represent a meaningful example, due to the presence of both convolutional (CONV) and transposed convolutional (TCONV) layers. While the former exploit multiply-and-accumulate (MAC) operations to extract features of interest from incoming feature maps (fmaps), the latter perform MACs to tune the spatial resolution of the received fmaps properly. The ever-growing real-time and low-power requirements of modern computer vision applications represent a stimulus for the research community to investigate the deployment of CNNs on well-suited hardware platforms, such as field programmable gate arrays (FPGAs). FPGAs are widely recognized as valid candidates for trading off computational speed and power consumption, thanks to their flexibility and their capability to also deal with computationally intensive models. In order to reduce the number of operations to be performed, this paper presents a novel hardware-oriented algorithm able to efficiently accelerate both CONVs and TCONVs. The proposed strategy was validated by employing it within a reconfigurable hardware accelerator purposely designed to adapt itself to different operating modes set at run-time. When characterized using the Xilinx XC7K410T FPGA device, the proposed accelerator achieved a throughput of up to 2022.2 GOPS and, in comparison to state-of-the-art competitors, it reached an energy efficiency up to 2.3 times higher, without compromising the overall accuracy.

A Mathematical Model for Determining the Composition of Binary Relations and an Algorithm for Binary Matrices Multiplication

Purpose of research. The need for the development of a mathematical model for determining the composition of binary relations and a hardware-oriented algorithm for multiplying binary matrices that allow organizing parallel data processing when determining the composition of binary relations.Methods. The procedure for determining the composition of binary relations is as follows: at the first stage, the definition of the sequence relation is performed, for this purpose its transitive closure is performed; the definition of the connection relation occurs after clarifying the sequence relation; then the alternative relation is clarified; at the final stage of determining the composition of binary relations, the parallelism relation is clarified.Results. In this paper, a mathematical model for determining the composition of binary relations and an algorithm for multiplying binary matrices are developed. The novelty of the mathematical model is the introduction of binary relations of connection, alternative and parallelism of the vertices of flowgraphs of parallel algorithms in addition to the sequence relation known in the graph theory. The novelty of the binary matrix multiplication algorithm is the reduction of the number of iterations of the inner cycle (with respect to the variable k) when obtaining a single value at one of the iterations of determining the scalar product of binary vectors.Conclusion. The developed mathematical model of binary relations of the sequence and connection of the vertices of flowgraphs of parallel algorithms allows for the organization of parallel data processing when determining the composition of binary relations. Based on the mathematical model for determining the composition of binary relations, a hardware-oriented algorithm for multiplying binary matrices was developed which allows transferring computationally complex procedures for multiplying binary matrices to the hardware level. The developed mathematical model and algorithm allow for the practical implementation of devices for multiplying binary matrices with an interruption of the internal cycle.

Fast hardware-oriented algorithm for 3D positioning in line-of-sight and single bounced non-line-of-sight environments

The ability to find the location of a mobile object and track it in two-dimensional (2D) and three-dimensional (3D) space is an indispensable feature of wireless communication systems. In particular, the increase in demand for using self-navigation technology in unmanned vehicles is attracting additional attention to this area of research. The methods and techniques developed for these systems compete in terms of simplicity, performance, and accuracy. However, the majority of solutions focus on only one of these performance metrics and are not applicable to the projected systems. In this study, a new location estimation solution that satisfies all three performance metrics (simplicity, accuracy, and efficiency) is achieved. The developed algorithms can be executed on a mobile object to allow it to learn its position in space. Furthermore, the simplicity of the mathematical operations used, namely binary shift and add operations, makes our algorithm hardware-friendly. Accelerated coordinate rotation digital computer (CORDIC) algorithms are used for the first time with line-of-sight (LOS) and single-bounced-scattering non-line-of-sight (SBS NLOS) signal arriving approaches for mobile object self-positioning. This study also introduces a newly developed 'vector-breaking' method (VBM) to estimate the location of a mobile object using the arriving signals from scatters with unknown locations. Test results using the developed algorithm show that the projected level of accuracy has been achieved. Furthermore, the developed algorithm performs better than the solutions currently available in the field.

Hardware-Oriented Algorithm for High-Speed Laser Centerline Extraction Based on Hessian Matrix

Centerline extraction is the basic and key procedure in line-structured laser 3-D scanners. In this article, we propose a hardware-oriented algorithm for fast and accurate extraction of a laser centerline based on the Hessian matrix. The algorithm is divided into three low-coupling modules that can be processed in parallel—coarse positioning, linewidth estimation, and precise positioning module. In the coarse positioning module, a window slider is used to traverse all image pixels in the raster-scan mode for collecting local image features, based on which the potential region of interest (ROI) containing laser lines is detected. In the linewidth estimation module, the second-order moment features in the detected ROI are calculated to estimate the linewidth according to the local rectangular similarity characteristics of the laser line. In the precise positioning module, the optimal Gaussian template estimated by the linewidth is convolved with the ROI to obtain the Hessian matrix. Based on the Hessian matrix, the normal direction of the laser line is obtained, and the second-order Taylor expansion is performed in that direction to determine the subpixel position of the center point. Finally, non-maximum suppression is used to remove noise points and obtain the most reliable single-pixel centerline. The proposed algorithm is evaluated using thousands of sample images with different materials, exposure times, and laser line shapes, and it presents high robustness for subpixel precision extraction. By implementing the proposed algorithm on a field-programmable gate array (FPGA), a high-speed, high-precision laser centerline extraction system is achieved, which operates at 1350 frames/s for a 1-million-pixel video stream.

Mathematical Model and Hardware-Oriented Algorithm for Programs Placement Planning in Systems on a Chip

Mathematical Model and Hardware-Oriented Algorithm for Programs Placement Planning in Systems on a Chip

An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots

This study develops an intelligent system for home service robots mimicking human brain function that can manage common knowledge applicable to any environment and local knowledge reflecting its specific environment. Deep learning is effective for acquiring common knowledge because the performance of deep learning relies on the amounts of training and big training data that can be accessed for such knowledge; however, deep learning is ineffective for acquiring local knowledge because no big training data for such knowledge exist. Thus, we propose a brain-inspired learning model and system for acquiring local knowledge using small training data. We focus on the amygdala because its classical fear conditioning is effective for training using small training data. We propose an amygdala-inspired classical conditioning model comprising multiple self-organizing maps (lateral nucleus) and a fully connected neural network (central nucleus), imitating the function and structure of the amygdala. The proposed model is applied to a task of a waiter robot in a restaurant, and the model can learn customers' preferences after only a few human-robot interactions. We accelerate the computation of the model and reduce its power consumption by proposing a hardware-oriented algorithm for the model and its digital hardware design and implement it in an XCZU9EG field programmable gate array. The hardware-oriented algorithm reduces the multiplication operations and exponential functions requiring huge hardware resources. The performance of the hardware operated at 150 MHz is 1,273 times faster than the software implementation on Arm Cortex-A53, and the power consumption of the chip is 5.009 W.

FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks

Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks

The Generation of $(n,n(n-1),n-1)$ Permutation Group Codes for Communication Systems

This paper concerns the construction and hardware execution of (n, n(n-1), n-1) permutation group codes (PGCs) for communication systems. Cyclic shift techniques acting on a permutation, including cyclic shift operators and their compound functions (CFs), are defined and demonstrated, then compared to other tools such as cyclic subgroups and n-dimension cyclic shift registers. A generalized finite state machine is established that can enumerate n! permutations based on complete CFs. This is a hardware-oriented algorithm that is capable of being significantly faster than all existing algorithms which we can find up to now. After this, the ideal structural features for an ordered set of n! permutations are discussed and the multiset features of (n, n(n-1), n-1)-PGCs in this ordered set are pinpointed. A simpler way of generating (n, n(n-1), n-1)-PGCs is then developed using cyclic shift techniques, where the code length n is a prime. This outperforms existing approaches using composite operation and affine transform on module-n operation. The simulation experiments in AWGN channel show that the performance on codeword error rates (WER) and signal-noise ratio (SNR) becomes better as the code length increases and the best SNR performance achieves −0.8 dB at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−5</sup> WER for code length n=11.

A Hardware-Oriented Algorithm for Ultra-High-Speed Object Detection

This paper describes a novel hardware-oriented algorithm that can be implemented on a field-programmable gate array in a high-speed vision platform for detection of multiple objects with clear texture information in images of $512\times 512$ pixels at 10 000 frames per second (fps) under complex background. The proposed algorithm is specially designed for devices with limited hardware resource for high-frame-rate, high-data-throughput, and high-parallelism processing of video streams with low latency. The proposed algorithm is based on the conventional histograms of oriented gradient (HOG) descriptor and support vector machine classifier algorithms. Considering the trade-off between speed and accuracy, many hardware-based optimization operations were implemented. The data throughput is nearly 29.30 Gbps while the latency for feature extraction is 0.76 us (61 clock period). After hardware-based image processing, the source image and the detected object features can be transferred to a personal computer for recording or post-processing at 10 000 fps. Several experiments were done to demonstrate the performance of our proposed algorithm for ultra-high-speed moving object detection with clear texture information in images.

Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials

Digit-serial systolic multipliers over $GF(2^m)$ based on the National Institute of Standards and Technology (NIST) recommended trinomials play a critical role in the real-time operations of cryptosystems. Systolic multipliers over $GF(2^m)$ involve a large number of registers of size $O(m^2)$ which results in significant increase in area complexity. In this paper, we propose a novel low register-complexity digit-serial trinomial-based finite field multiplier. The proposed architecture is derived through two novel coherent interdependent stages: (i) derivation of an efficient hardware-oriented algorithm based on a novel input-operand feeding scheme and (ii) appropriate design of novel low register-complexity systolic structure based on the proposed algorithm. The extension of the proposed design to Karatsuba algorithm (KA)-based structure is also presented. The proposed design is synthesized for FPGA implementation and it is shown that it (the design based on regular multiplication process) could achieve more than 12.1 percent saving in area-delay product and nearly 2.8 percent saving in power-delay product. To the best of the authors’ knowledge, the register-complexity of proposed structure is so far the least among the competing designs for trinomial based systolic multipliers (for the same type of multiplication algorithm).

A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation

High Efficiency Video Coding (HEVC), the latest video coding standard, aims to provide coding performance that is much superior to that of its predecessor, H.264, especially for high definition video. To fulfill this goal, the inter-prediction unit (PU) partitions of HEVC are more complex, and the search range of motion estimation (ME) is much larger. As a result, ME becomes a bottleneck in the design of the HEVC inter predictor. In response to this challenge, we developed a hardware-oriented integer ME algorithm and the related hardware implementation. Our proposed algorithm led to a decrease in terms of the Bjontegaard Delta rate when compared with the HEVC test model 15.0. The corresponding hardware solution benefitted from 2-D data reuse supported by horizontal and vertical reference SRAMs, on-chip memory reduction supported by $4\times4$ block compression, and a low-power sum of absolute difference (SAD) tree supported by PU-level chip selection. When adopting a $32\times32$ SAD tree, the minimum and maximum required working frequency for 4K $\times2\text{K}$ at 30 frames/s videos was [375, 500] MHz. These results demonstrated that our proposed solution offered desirable improvement in both coding speed and coding performance.

Hardware Accelerator for the Multifractal Analysis of DNA Sequences.

The multifractal analysis has allowed to quantify the genetic variability and non-linear stability along the human genome sequence. It has some implications in explaining several genetic diseases given by some chromosome abnormalities, among other genetic particularities. The multifractal analysis of a genome is carried out by dividing the complete DNA sequence in smaller fragments and calculating the generalized dimension spectrum of each fragment using the chaos game representation and the box-counting method. This is a time consuming process because it involves the processing of large data sets using floating-point representation. In order to reduce the computation time, we designed an application-specific processor, here called multifractal processor, which is based on our proposed hardware-oriented algorithm for calculating efficiently the generalized dimension spectrum of DNA sequences. The multifractal processor was implemented on a low-cost SoC-FPGA and was verified by processing a complete human genome. The execution time and numeric results of the Multifractal processor were compared with the results obtained from the software implementation executed in a 20-core workstation, achieving a speed up of 2.6x and an average error of 0.0003 percent.

A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries’ speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but highperformance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

Fully pipelined CORDIC‐based inverse kinematic FPGA design for biped robots

A high-speed field-programmable gate array (FPGA) design is proposed to calculate angles and distances for biped robots in real time. A low-complexity and high-accuracy hardware-oriented algorithm based on CORDIC was developed. To reduce hardware cost, a hardware sharing technique was used to realise a CORDIC scaling factor generator and three hardware sharing machines. Moreover, the multipliers and dividers were replaced by cost-efficiency components, such as adders and shifters to further reduce hardware cost. In addition, the proposed design was implemented with a fully pipelined architecture, which achieved improved operating frequency and throughput efficiency. The proposed design was realised and verified by an FPGA device with a maximum operating frequency of 127 MHz, which achieved the calculation of angles and distances for biped robots in real time. Compared with the previous design, this work not only reduced hardware cost by at least 49.6% and average errors by at least 67.2%, but also improved the average executing performance by 62.7% when calculating ten angles for the biped robots.

A Hardware-oriented Algorithm for Complex-valued Constant Matrix-vector Multiplication.

In this paper we present a hardware-oriented algorithm for constant matrix-vector product calculating, when the all elements of vector and matrix are complex numbers. The proposed algorithm versus the naive method of analogous calculations drastically reduces the number of multipliers required for FPGA implementation of complex-valued constant matrix-vector multiplication.If the fully parallel hardware implementation of naive (schoolbook) method for complex-valued matrix-vector multiplication requires 4MN multipliers, 2M N-inputs adders and 2MN two-input adders, the proposed algorithm requires only 3N(M+1)/2 multipliers and 3M(N+2)+1,5N+2 two-input adders and 3(M+1) N/2-input adders.

Hardware-Oriented Algorithm for Quaternion-Valued Matrix Decomposition

In this brief, a generalized form for 2-, 4-, and 8-D coordinate rotation digital computer (CORDIC) rotation matrices is suggested, and a novel highly parallel efficient hardware-oriented 8-D octonion CORDIC algorithm for quaternion-valued matrix decomposition is designed and presented. Furthermore, a successful sequence of iterations with guaranteed convergence is determined, and the hardware implementation of this algorithm is considered. Such a processor can be utilized to speed up the Givens rotations and computing the QR and singular-value decomposition processes of a quaternion matrix in a digital signal processor.

Hardware-Oriented Early Detection Algorithms for 4*4 and 8*8 All-Zero Blocks in H.264

H.264 is the latest HDTV video compression standard, which provides a significant improvement in coding efficiency at the cost of huge computation complexity. After transform and quantization, if all the coefficients of the block's residue data are zero, this block is called all-zero block (AZB). Provided that an AZB can be detected early, the process of transform and quantization on an AZB can be skipped, which reduces significant redundant computations. In this paper, a theoretical analysis is performed for the sufficient condition for AZB detection. As a result, a partial sum of absolute difference (SAD) based 4 × 4 AZB detection algorithm is derived. And then, a hardware-oriented AZB detection algorithm is proposed by modifying the order of SAD calculation. Furthermore, a quantization parameter (QP) oriented 8 × 8 AZB detection algorithm is proposed according to the AZB's statistical analysis. Experimental results show that the proposed algorithm outperforms the previous methods in all cases and achieves major improvement of computation reduction in the range from 6.7% to 42.3% for 4 × 4 blocks, from 0.24% to 79.48% for 8 × 8 blocks. The computation reduction increases as QP increases.