Hardware Operating System Research Articles

Unveiling the core of IoT: comprehensive review on data security challenges and mitigation strategies

The Internet of Things (IoT) is a collection of devices such as sensors for collecting data, actuators that perform mechanical actions on the sensor's collected data, and gateways used as an interface for effective communication with the external world. The IoT has been successfully applied to various fields, from small households to large industries. The IoT environment consists of heterogeneous networks and billions of devices increasing daily, making the system more complex and this need for privacy and security of IoT devices become a major concern. The critical components of IoT are device identification, a large number of sensors, hardware operating systems, and IoT semantics and services. The layers of a core IoT application are presented in this paper with the protocols used in each layer. The security challenges at various IoT layers are unveiled in this review paper along with the existing mitigation strategies such as machine learning, deep learning, lightweight encryption techniques, and Intrusion Detection Systems (IDS) to overcome these security challenges and future scope. It has been concluded after doing an intensive review that Spoofing and Distributed Denial of Service (DDoS) attacks are two of the most common attacks in IoT applications. While spoofing tricks systems by impersonating devices, DDoS attacks flood IoT systems with traffic. IoT security is also compromised by other attacks, such as botnet attacks, man-in-middle attacks etc. which call for strong defenses including IDS framework, deep neural networks, and multifactor authentication system.

Reshaping healthcare with wearable biosensors

Wearable health sensors could monitor the wearer's health and surrounding environment in real-time. With the development of sensor and operating system hardware technology, the functions of wearable devices have been gradually enriched with more diversified forms and more accurate physiological indicators. These sensors are moving towards high precision, continuity, and comfort, making great contributions to improving personalized health care. At the same time, in the context of the rapid development of the Internet of Things, the ubiquitous regulatory capabilities have been released. Some sensor chips are equipped with data readout and signal conditioning circuits, and a wireless communication module for transmitting data to computer equipment. At the same time, for data analysis of wearable health sensors, most companies use artificial neural networks (ANN). In addition, artificial neural networks could help users effectively get relevant health feedback. Through the physiological response of the human body, various sensors worn could effectively transmit data to the control unit, which analyzes the data and provides feedback of the health value to the user through the computer. This is the working principle of wearable sensors for health. This article focuses on wearable biosensors used for healthcare monitoring in different situations, as well as the development, technology, business, ethics, and future of wearable sensors for health monitoring.

An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems

<p>Several embedded application domains for reconfigurable systems tend to combine <br />frequent changes with high performance demands of their workloads such as image processing, wearable computing and<br />network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging <br />from run-time systems to complex programming models that usually form a Reconfigurable<br />hardware Operating System (ROS). The Operating System performs online task scheduling and handles resource management.<br />There are many challenges in adaptive computing and dynamic reconfigurable systems. One of the major understudied challenges<br />is estimating the required resources in terms of soft cores, Programmable Reconfigurable Regions (PRRs), <br />the appropriate communication infrastructure, and to predict a near optimal layout and floor-plan of the reconfigurable logic fabric. <br />Some of these issues are specific to the application being designed, while others are more general and relate to the underlying run-time environment.<br />Static resource allocation for Run-Time Reconfiguration (RTR) often leads to inferior and unacceptable results. <br />In this paper, we present a novel adaptive and dynamic methodology, based on a Machine Learning approach, for predicting and<br />estimating the necessary resources for an application based on past historical information.<br />An important feature of the proposed methodology is that the system is able to learn and generalize and, therefore, is expected to improve <br />its accuracy over time. The goal of the entire process is to extract useful hidden knowledge from the data. This knowledge is the prediction <br />and estimation of the necessary resources for an unknown or not previously seen application.<br /><br /></p>

Design of Intelligent Power Management System Based on Internet of Things

Intelligent power management system based on Internet of things is mainly used in electrical equipment focused occasions such as home or office, used for remote monitoring and managing the power of the electrical equipment, the system also has intelligent management functionality, it can control power supply based on current state of the power consumption of the electrical equipment, to achieve the purpose of saving energy consumption. The control center of the system used embedded hardware platform and Linux operating systems based on the ARM processor core, software development used C language.In this paper, the overall design of the system is described.

REAL TIME DATA PROCESSING FOR OPTICAL REMOTE SENSING PAYLOADS

Abstract. The application of operational systems for remote sensing requires new approaches for data processing. It has to be the goal to derive user relevant information close the sensor itself and to downlink this information to a ground station or to provide them as input to an actuator of the space-borne platform. A complete automation of data processing is an essential first step for a thematic onboard data processing. In a second step, an appropriate onboard computer system has to be de-signed being able to fulfill the requirements. In this paper, standard data processing steps will be introduced correcting systematic errors during image capturing. A new hardware operating system, which is the interface between FPGA hardware and data processing algorithms, gives the opportunity to implement complex data processing modules in an effective way. As an example the derivation the camera's orientation based on data of an optical payload is described in detail. The thereby derived absolute or relative orientation is essential for high level data products. This will be illustrated by means of an onboard image matcher

IPS – A SYSTEM FOR REAL-TIME NAVIGATION AND 3D MODELING

Abstract. fdaReliable navigation and 3D modeling is a necessary requirement for any autonomous system in real world scenarios. German Aerospace Center (DLR) developed a system providing precise information about local position and orientation of a mobile platform as well as three-dimensional information about its environment in real-time. This system, called Integral Positioning System (IPS) can be applied for indoor environments and outdoor environments. To achieve high precision, reliability, integrity and availability a multi-sensor approach was chosen. The important role of sensor data synchronization, system calibration and spatial referencing is emphasized because the data from several sensors has to be fused using a Kalman filter. A hardware operating system (HW-OS) is presented, that facilitates the low-level integration of different interfaces. The benefit of this approach is an increased precision of synchronization at the expense of additional engineering costs. It will be shown that the additional effort is leveraged by the new design concept since the HW-OS methodology allows a proven, flexible and fast design process, a high re-usability of common components and consequently a higher reliability within the low-level sensor fusion. Another main focus of the paper is on IPS software. The DLR developed, implemented and tested a flexible and extensible software concept for data grabbing, efficient data handling, data preprocessing (e.g. image rectification) being essential for thematic data processing. Standard outputs of IPS are a trajectory of the moving platform and a high density 3D point cloud of the current environment. This information is provided in real-time. Based on these results, information processing on more abstract levels can be executed.

The Design of Embedded AeroEngine Measurement and Test System Based on ARM and FPGA

Present Measurement and test system for aeroengine rig testing is primarily based on DSP and PC104 industrial computer, which have the disadvantages of large volume, high power consumption, single function and less-generic. So it is a valuable job to promote the performance of the system employing the latest methods of collaborative design and embedded hardware and software technology. For designing of the new type improved aeroengine test system, a hardware and software co-design strategy is employed. After a thorough trade-off analysis and comparison among different hardware and software systems, an embedded aeroengine test system based on ARM and FPGA is designed, by using S3C2440A CPU with ARM920T core and FPGA from Xilinx as fundamental hardware data acquisition and process platform, using Linux as real time operating system. The data transmission between ARM and FPGA take the path of dual-port RAM, during which the read-write operation is coordinated by means of interruption. The system uses U-Boot to initialize hardware and load operating system. FPGA is used as foreside of data acquisition system, which sampling parameter setting is loaded by reading configuration file during start-up and read into inner register by SPI bus. Data is exported from flash-chip of test system by means of U-disk or network, and analyzed in PC equipped with specialized software. Strong post-proceeding capacity for multi parameters of aeroengine rig testing can be realized, especially for dynamic signal analysis in time domain, frequency domain. Because of the use of the new platform, a big promotion has been achieved. I) the capacity of data processing increases by 15%. II) The new system allows numbers of the sampling channels to double. III) Abundant functions of software can realize more professional, intelligent and generic tests. IV) Sampling frequencies increases by 20%, meeting the demand of monitoring dynamic random signals such as noise and vibration, on fluctuating pressure with wide frequency band. The embedded aeroengine test system based on ARM and FPGA is successful and the prototype is manufactured and tested. It is found that the performance of the new system is promoted significantly, which shows the effectiveness and reliability of the method employed.

A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models

HD video applications can be represented with multiple tasks consisting of tightly coupled multiple threads. Each task requires massive computation, and their communication can be categorized as asynchronous distributed small data and large streaming data transfers. In this paper, we propose a high performance programmable video platform that consists of four processing element (PE) clusters. Each PE cluster runs a task in the video application with RISC cores, a hardware operating system kernel (HOSK), and task-specific accelerators. PE clusters are connected with two separate point-to-point networks: one for asynchronous distributed controls and the other for heavy streaming data transfers among the tasks. Furthermore, we developed an application mapping framework, with which parallel executable codes can be obtained from a manually developed SystemC model of the target application without knowing the detailed architecture of the video platform. To show the effectivity of the platform and its mapping framework, we also present mapping results for an H.264/AVC 720p decoder/encoder and a VC-1 720p decoder with 30 fps, assuming that the platform operates at 200MHz.

A hardware operating system kernel for multi-processor systems

A hardware operating system kernel for multi-processor systems

Tasking Distributed Sensor Networks

Distributed wireless sensor networks provide significant new capabilities for automatically collecting and analyzing data from physical environments. Such sensor networks gather and analyze data in response to queries posed by users of the network. By using more sensor nodes than is strictly necessary to cover an area, these sensor networks can provide reliable information, tolerate many types of faults, and have a long effective lifetime. Like most wireless systems, however, these sensor networks must effectively manage power consumption to achieve a satisfactory system lifetime. Power management at the node level, including low power hardware and power aware operating systems, can provide significant savings in power consumption. In this paper, we present algorithms for managing power at the distributed system level, rather than just at the individual node level. These distributed algorithms determine which set of sensor nodes will be tasked with a given user query and which sensor nodes will remain in an idle state conserving power. The goal of the algorithms is to extend the effective service time of the entire network. In this paper, we give a theoretical analysis of these algorithms along with extensive simulation results.

Internet Technologies for Improving Data Access

The term “Internet technologies” has recently been coined to describe a set of software capabilities aimed at improving data communications and data access in contemporary enterprise information systems. This article presents a framework for implementing Internet technologies to improve enterprisewide data access, particularly in terms of the user interface, communications networking, the application platform, and the hardware operating systems platform. Examples of software products are given to illustrate how Internet technologies affect these platforms.

Experience with building a commodity Intel-based ccNUMA system

Commercial cache-coherent nonuniform memory access (ccNUMA) systems often require extensive investments in hardware design and operating system support. A different approach to building these systems is to use Standard High Volume (SHV) hardware and stock software components as building blocks and assemble them with minimal investments in hardware and software. This design approach trades the performance advantages of specialized hardware design for simplicity and implementation speed, and relies on application-level tuning for scalability and performance. We present our experience with this approach in this paper. We built a 16-way ccNUMA Intel system consisting of four commodity four-processor Fujitsu® Teamserver™ SMPs connected by a Synfinity™ cache-coherent switch. The system features a total of sixteen 350-MHz Intel® Xeon™ processors and 4 GB of physical memory, and runs the standard commercial Microsoft Windows NT® operating system. The system can be partitioned statically or dynamically, and uses an innovative, combined hardware/software approach to support application-level performance tuning. On the hardware side, a programmable performance-monitor card measures the frequency of remote-memory accesses, which constitute the predominant source of performance overhead. The monitor does not cause any performance overhead and can be deployed in production mode, providing the possibility for dynamic performance tuning if the application workload changes over time. On the software side, the Resource Set abstraction allows application-level threads to improve performance and scalability by specifying their execution and memory affinity across the ccNUMA system. Results from a performance-evaluation study confirm the success of the combined hardware/software approach for performance tuning in computation-intensive workloads. The results also show that the poor local-memory bandwidth in commodity Intel-based systems, rather than the latency of remote-memory access, is often the main contributor to poor scalability and performance. The contributions of this work can be summarized as follows: • The Resource Set abstraction allows control over resource allocation in a portable manner across ccNUMA architectures; we describe how it was implemented without modifying the operating system. • An innovative hardware design for a programmable performance-monitor card is designed specifically for a ccNUMA environment and allows dynamic, adaptive performance optimizations. • A performance study shows that performance and scalability are often limited by the local-memory bandwidth rather than by the effects of remote-memory access in an Intel-based architecture.

Architectures for secure portable executable content

The Java programming language supports the concept of downloadable executable content; a key technology in a wide range of emerging applications including collaborative systems, electronic commerce, and Web information services. Java enables the execution of a program, on almost any modern computer regardless of hardware configuration and operating system. Safe‐Tcl was proposed as an executable content type of MIME and thus as the standard language for executable contents within e‐mail messages. However, the ability to download, integrate, and execute code from a remote computer, provided by both Java and Safe‐Tcl, introduces serious security risks since it enables a malicious remote program to obtain unauthorised access to the downloading system’s resources. In this paper, the two proposed security models are described in detail and the efficiency and flexibility of current implementations are evaluated in a comparative manner. Finally, upcoming extensions are discussed.

Technical Issues Related to Digital Stress Echocardiography Analysis and Acquisition Stations.

Digital acquisition and display of echocardiographic images has facilitated the development of stress echocardiography. This review will outline technical issues involved with digital capture and manipulation of echocardiographic data, referring to currently available commercial equipment. Among the acquisition items to be discussed are the source of the digitized data (direct digital transfer from the echo machine vs video capture); image resolution (spatial and temporal spacing of the digitized data); and EKG triggering options (direct triggering of the QRS complex vs detecting the QRS on the video transfer). During playback, rest and stress images may be displayed at different frame rates, so that systole will occupy approximately the same time interval. Currently available commercial systems are compared with regard to these features, as well as hardware architecture and operating system.

Quantitative analysis of hardware support for real-time operating systems

Microprocessor architects, supported by advances in VLSI technology, have been enormously successful at steadily accelerating the performance of application software. However, operating system performance has lagged due to a divergence between operating system and architectural trends. Unfortunately, some recent work in this area has targeted average-case performance improvements with little or no consideration for the worst-case behavior that must be considered for real-time applications. This paper explores whether one can improve the worst-case performance of operating systems, and as a result, the schedulability of real-time task-sets, using specific hardware-assisted operating system primitives without sacrificing flexibility. The Intel 80960XA Microprocessor, which directly supports basic operating system primitives in hardware, provides an excellent platform to explore operating system hardware and software boundary issues. This paper specifically analyzes the viability of an hardware-assisted fixed-priority scheduler. Using the Real-Time Mach operating system, we did two ports to the 80960XA: one representative of generic RISC implementations, and another which exploited the hardware-supported operating system primitives. We measured the performance of the operating system primitives in both cases and found an average performance improvement factor of 3 for the hardware accelerated version. We applied a formal scheduling model to evaluate the relative performance of the two implementations for two representative real-time applications. The hardware accelerated version reduced operating system burden by factors of 2.66 and 4.1 for the avionics and inertial navigational system task sets, respectively.

The Control System for the Dedicated Synchrotron Radiation Storage Ring Bessy

BESSY is a 800 MeV electron-storage ring dedicated to research with synchrotron radiation in the VUV and soft X-ray region. The storage ring is fed by a 800 MeV separated function synchrotron with a clasical 20 MeV microtron as preinjector. The machines are remotely controlled by four minicomputers which are linked by a local network. The computers are connected to a commercially available electronic interface system. The general philosophy for the system design was determined by boundary conditions such as reliable processor hardware, reliable and powerful multi-user multi-programming real-time operating systems, well developed software tools, a ready-to-use distributed network with high throughput, compatibility of the electronic interface system, locally available service shops, and, if possible, the avoidance of assembly coding. This paper describes in detail the system which ultimately met these criteria and was subsequently implemented at BESSY.

Development of Display Design and Command Usage Guidelines for Spacelab Experiment Computer Applications

Individual Spacelab experimenters are responsible for developing their CRT display formats and interactive command scenarios for payload crew monitoring and control of experiment operations via the Spacelab Data Display System (DDS). In order to enhance crew training and flight operations, it was important to establish some standardization of the crew/experiment interface among different experiments by providing standard methods and techniques for data presentation and experiment commanding via the DDS. In order to establish optimum usage guidelines for the Spacelab DDS, the capabilities and limitations of the hardware and Experiment Computer Operating System design had to be considered. Since the operating system software and hardware ware design had already been established, the Display and Command Usage Guidelines were constrained to the capabilities of the existing system design. Empirical evaluations were conducted on a DDS simulator to determine optimum operator/system interface utilization of the system capabilities. Display parameters such as information location, display density, data organization, status presentation and dynamic update effects were evaluated in terms of response times and error rates.