Hardware Mechanisms Research Articles

Design of a traction neck brace with two degrees-of-freedom via a novel architecture of a spatial parallel mechanism

Abstract Traction of the head-neck is important in the treatment of patients suffering from neck pain due to degeneration of the intervertebral discs. Conventional neck traction is provided manually by experienced physical therapists who maintain a desired orientation of the head-neck relative to the trunk while applying the traction. It is postulated that innovative designs of neck exoskeletons can provide the same function both flexibly and accurately. This article presents a novel architecture of a parallel mechanism whose base sits on the human shoulders with 4 parallel chains, each chain having a revolute-revolute-universal-revolute (RRUR) structure, while the end-effector is connected rigidly to the human head. Each chain has five degrees-of-freedom (DOF) and applies a constraint on the motion of the end-effector. As a result, this parallel mechanism allows two DOFs to the end-effector. These are (i) forward flexion or lateral bending of the head and (ii) vertical translation. An important motivation for the current design with RRUR structure is to characterize the range of forward flexion/lateral bending of the head-neck with this structure and the vertical translation to the end-effector. A physical prototype was constructed and tested to evaluate the performance of this mechanism in hardware for the proposed application.

Strategies for Promoting Rural Digital Party Building from the Perspective of Rural Governance

With the rapid development of digital internet technology, digital party building has gradually developed and become a hot issue in academic circles. The countryside is a late-developing place for the popularization of digital model. Digitalization has brought technical advantages to rural party building, such as online information and data, collaborative information resources and accurate party building services. However, at present, rural areas are facing problems such as weak "key nodes", digital gap, imperfect operation mechanism and insufficient investment in software and hardware. In the new development stage, rural digital party building should: strengthen the "key nodes" of digital party building; Focus on solving the "digital divide" problem; Improve the operation mechanism of rural digital party building; Increase the capital investment in rural digital party building, so as to implement the work of digital party building and improve the governance efficiency of rural party organizations.

Rewards, risks and responsible deployment of artificial intelligence in water systems

Artificial intelligence (AI) is increasingly proposed to address deficiencies across water systems, which currently leave about 25% of the global population without clean water, about 50% without sanitation services and about 30% without hygiene facilities. AI is poised to enhance supply insights, catchment management and emergency response, improve treatment plant and distribution network design, operation and maintenance, and advance service availability, demand management and water justice. However, proliferation of this nascent technology could trigger serious and unexpected problems, including system-wide compromise owing to design errors, malfunction and cyberattacks as well as exposures to cascading socio-ecological, water–energy–food nexus and coupled critical infrastructure failures. In response, we make three recommendations for safe and responsible deployment of AI across potable water supply and sewage disposal systems: address gaps in foundational infrastructure and digital literacy; establish institutional, software and hardware mechanisms for trustworthy AI; and prioritize applications based on our proposed systematic benefit and risk assessment framework. In this Perspective, the authors survey potential water-system-wide benefits of AI applications from catchments to end-users and then highlight potential systemic barriers, direct risks and exposures to cascading failures, which may prove catastrophic for communities. In response, they make three recommendations for safe and responsible deployment of AI across potable water supply and sewage disposal systems.

Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison

Precise event sampling is a profiling feature in commodity processors that can sample hardware events and accurately locate the instructions that trigger the events. This feature has been used in a large number of tools to detect application performance issues. Although precise event sampling is readily supported in modern multicore architectures, vendor supports exhibit great differences that affect their accuracy, stability, overhead, and functionality. This work presents the most comprehensive study to date on benchmarking the event sampling features of Intel PEBS and AMD IBS and performs in-depth analysis on key differences through series of microbenchmarks. Our qualitative and quantitative analysis shows that PEBS allows finer-grained and more accurate sampling of hardware events, while IBS offers richer set of information at each sample though it suffers from lower accuracy and stability. Moreover, OS signal delivery, which is a common method used by the profiling software, introduces significant time overhead to the original overhead incurred by the hardware mechanisms in both PEBS and IBS. We also found that both PEBS and IBS have bias in sampling events across multiple different locations in a code. Lastly, we demonstrate how our findings on microbenchmarks under different thread counts hold for a full-fledged profiling tool that runs on the state-of-the-art Intel and AMD machines. Overall our detailed comparisons serve as a great reference and provide invaluable information for hardware designers and profiling tool developers.

An Adaptive Simultaneous Multi-Protocol Extension of CRAFT.

An exponential number of devices connect to Internet of Things (IoT) networks every year, increasing the available targets for attackers. Protecting such networks and devices against cyberattacks is still a major concern. A proposed solution to increase trust in IoT devices and networks is remote attestation. Remote attestation establishes two categories of devices, verifiers and provers. Provers must send an attestation to verifiers when requested or at regular intervals to maintain trust by proving their integrity. Remote attestation solutions exist within three categories: software, hardware and hybrid attestation. However, these solutions usually have limited use-cases. For instance, hardware mechanisms should be used but cannot be used alone, and software protocols are usually efficient in particular contexts, such as small networks or mobile networks. More recently, frameworks such as CRAFT have been proposed. Such frameworks enable the use of any attestation protocol within any network. However, as these frameworks are still recent, there is still considerable room for improvement. In this paper, we improve CRAFT's flexibility and security by proposing ASMP (adaptative simultaneous multi-protocol) features. These features fully enable the use of multiple remote attestation protocols for any devices. They also enable devices to seamlessly switch protocols at any time depending on factors such as the environment, context, and neighboring devices. A comprehensive evaluation of these features in a real-world scenario and use-cases demonstrates that they improve CRAFT's flexibility and security with minimal impact on performance.

An Energy-Efficient Domain-Specific Architecture for Regular Expressions

Regular Expressions (REs) are a computational kernel widely used for finding patterns in data in compute-intensive tasks such as genomic markers research, signature-based detection, and database query. Although flexible on the set of searched REs, software-based solutions cannot fulfill latency or throughput requirements to analyze massive data volumes at a given power budget. For this reason, many approaches exploit hardware accelerators as an offloading engine for REs matching. Indeed, various solutions rely on FPGA reconfigurability to embed automata into the reconfigurable fabric. However, this approach leads to time-consuming updates of the REs to search. This work exploits REs as sequences of basic instructions and builds a Domain-Specific Architecture (DSA), called \tirex, for RE matching on FPGAs. Our approach enables the user to change the desired RE at run-time, providing software programmability, flexibility, and specialized hardware mechanisms. Our DSA delivers performance in line with other state-of-the-art hardware approaches, while providing remarkable flexibility and we underline the importance of energy efficiency for these computations. We compared with multiple state-of-the-art software obtaining remarkable performance while achieving noticeable results with a better energy efficiency that ranges from 3x to 490x with our multi-core.

Концептуальный подход к классификации и сертификации роботов и сложных автоматизированных информационных систем

Introduction. The development and spread of robots, artificial intelligence systems and complex automated information systems are associated with the problem of causing harm by their decisions and actions, as well as the problem of legal liability for this harm. Theoretical analysis. One of the main functions of legal liability is general and private prevention. When applied to robots, it requires them to be reprogrammed, retrained, or eliminated. Thus, the issue of the possibility, forms and conditions of their existence is directly related to the problem of legal responsibility of autonomous and sometimes unpredictable software and hardware mechanisms. A systemic legal structure aimed at ensuring safety and predictability in the creation and operation of robots can be built on the basis of a classifying standard, and each class will be associated with certain forms and models of responsibility. Empirical analysis. The basis of the legal classification of robots and complex automated information systems will be the threats associated with causing harm as a result of their spontaneous actions and decisions, correlated with the forms of legal liability. The following threats can be identified: causing the death of a person; unlawful change in the legal status of the subject; causing material harm; violation of the personal non-property rights of a person; information or other property of the owner (user), not related to causing harm to third parties; the threat of illegal behavior of robots. Results. The authors propose a classification of robots and complex automated systems, as well as approaches to legal liability and security for each class, and indicate directions for promising development of legal and technical standards necessary to ensure this classification and certification.

A noninterference trusted dual system security guarantee method based on secure memory

SummaryWith the continuous maturity and development of single hardware security mechanism, it has been widely used in the field of information technology, but the single hardware mechanism has insufficient security guarantee in its own supporting drivers and other key programs. In response to this problem, this article proposes a trusted isolation model based on the noninterference theory and gives a formal proof. The realization is based on the trusted platform control module (TPCM) hardware mechanism by introducing a secure memory bar to provide a way to achieve a trusted dual‐system isolation guarantee. The hardware interface of secure memory module is consistent with that of ordinary memory module, which is widely used. It can improve the security guarantee ability of trusted computing platform, and has a good reference value for the design and application of trusted computing platform equipment.

Segmented Spline Curve Neural Network for Low Latency Digital Predistortion of RF Power Amplifiers

At present, we are the dawn of a new era for wireless communication systems. The new dynamic approach to the operation of cellular networks requires an extension of the essential input–output hardware mechanisms, to include intelligence. Traditional neural network structures can be used to embed artificial intelligence into cellular network base stations; however, standard network structures are not an optimal solution for these use cases. In this article, we present a neural network structure, which is specifically designed to provide a more accurate and computationally efficient solution compared with the previous neural network solutions for predistortion of RF power amplifiers (PAs). The proposed network structure is directly compared with alternative neural network solutions, which have been successfully employed for digital predistortion (DPD). The operation of this network is validated for DPD with experimental measurements with wideband signals using the latest generation of commercially available RF hardware. The novel network structure proposed in this work is demonstrated, in practice, to have better performance for a normalized mean square error (NMSE), an adjacent channel leakage ratio (ACLR), and an error vector magnitude (EVM) compared with the most popular previously published neural network.

Behind the last line of defense: Surviving SoC faults and intrusions

Today, leveraging the enormous modular power, diversity and flexibility of manycore systems-on-a-chip (SoCs) requires careful orchestration of complex and heterogeneous resources, a task left to low-level software, e.g., hypervisors. In current architectures, this software forms a single point of failure and worthwhile target for attacks: once compromised, adversaries can gain access to all information and full control over the platform and the environment it controls. This article proposes Midir, an enhanced manycore architecture, effecting a paradigm shift from SoCs to distributed SoCs. Midir changes the way platform resources are controlled, by retrofitting tile-based fault containment through well known mechanisms, while securing low-overhead quorum-based consensus on all critical operations, in particular privilege management and, thus, management of containment domains. Allowing versatile redundancy management, Midir promotes resilience for all software levels, including at low level. We explain this architecture, its associated algorithms and hardware mechanisms and show, for the example of a Byzantine fault tolerant microhypervisor, that it outperforms the highly efficient MinBFT by one order of magnitude.

Design and Testing of a Computer Security Layer for the LIN Bus.

Most modern vehicles are connected to the internet via cellular networks for navigation, assistance, etc. via their onboard computer, which can also provide onboard Wi-Fi and Bluetooth services. The main in-vehicle communication buses (CAN, LIN, FlexRay) converge at the vehicle’s onboard computer and offer no computer security features to protect the communication between nodes, thus being highly vulnerable to local and remote cyberattacks which target the onboard computer and/or the vehicle’s electronic control units through the aforementioned buses. To date, several computer security proposals for CAN and FlexRay buses have been published; a formal computer security proposal for the LIN bus communications has not been presented. So, we researched possible security mechanisms suitable for this bus’s particularities, tested those mechanisms in microcontroller and PSoC hardware, and developed a prototype LIN network using PSoC nodes programmed with computer security features. This work presents a novel combination of encryption and a hash-based message authentication code (HMAC) scheme with replay attack rejection for the LIN communications. The obtained results are promising and show the feasibility of the implementation of an LIN network with real-time computer security protection.

FPGA-based design and implementation of the location attention mechanism in neural networks

The location attention mechanism has been widely applied in deep neural networks. However, as the mechanism entails heavy computing workload, significant memories consumed for weights storage, and shows poor parallelism in some calculations, it is hard to achieve high efficiency deployment. In this paper, the field-programmable gate array (FPGA) is employed to implement the location attention mechanism in hardware, and a novel fusion approach is proposed to connect the convolutional layer with the fully connected layer, which not only improves the parallelism of both the algorithm and the hardware pipeline, but also reduces the computation cost for such operations as multiplication and addition. Meanwhile, the shared computing architecture is used to reduce the demand for hardware resources. Parallel computing arrays are utilized to time-multiplex a single computing array, which can speed up the pipeline parallel computing of the attention mechanism. Experimental results show that for the location attention mechanism, the FPGA’s inference speed is 0.010 ms, which is around a quarter of the speed achieved by running it with GPU, and its power consumption is 1.73 W, which is about 2.89% of the power consumed by running it with CPU. Compared with other FPGA implementation methods of attention mechanism, it has less hardware resource consumption and less inference time. When applied to speech recognition tasks, the trained attention model is symmetrically quantized and deployed on the FPGA. The result shows that the word error rate is only 0.79% higher than that before quantization, which proves the effectiveness and correctness of the hardware circuit.

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems

Future CPU-manycore heterogeneous systems can provide high peak throughput by integrating thousands of simple, independent, energy-efficient cores in a single die. However, there are two key challenges to translating this high peak throughput into improved end-to-end workload performance: (1) manycore co-processors rely on simple hardware putting significant demands on the software programmer; and (2) manycore co-processors use in-order cores that struggle to tolerate long memory latencies. To address the manycore programmability challenge, this paper presents a dense and sparse tensor processing framework based on PyTorch that enables domain experts to easily accelerate off-the-shelf workloads on CPUmanycore heterogeneous systems. To address the manycore memory latency challenge, we use our extended PyTorch framework to explore the potential for decoupled access/execute (DAE) software and hardware mechanisms. More specifically, we propose two software-only techniques, naive-software DAE and systolic-software DAE, along with a lightweight hardware access accelerator to further improve area-normalized throughput. We evaluate our techniques using a combination of PyTorch operator microbenchmarking and real-world PyTorch workloads running on a detailed register-transfer-level model of a 128-core manycore architecture. Our evaluation on three real-world dense and sparse tensor workloads suggest these workloads can achieve approximately 2-6× performance improvement when scaled to a future 2,000-core CPU-manycore heterogeneous system compared to an 18-core out-of-order CPU baseline, while potentially achieving higher area-normalized throughput and improved energyefficiency compared to general-purpose graphics processing units.

Dynamic fault-tolerant VLIW processor with heterogeneous Function Units

Instruction Level Parallelism (ILP) of applications is typically limited and variant in time, thus during application execution some processor Function Units (FUs) may not be used all the time. Therefore, these idle FUs can be used to execute replicated instructions, improving reliability. However, existing approaches either schedule the execution of replicated instructions based on compiler schedule or consider processors with identical FUs, able to execute any instruction type. The former approach has a negative impact on performance, whereas the later approach is not applicable on processors with heterogeneous FUs. This work presents a hardware mechanism for processors with heterogeneous FUs that dynamically replicates instructions and schedules both original and replicated instructions considering space and time scheduling. The proposed approach uses a small scheduling window of two cycles, leading to a hardware mechanism with small hardware area. In order to perform such a flexible dynamic instruction scheduling, switches are required, which, however, increase the hardware area. To reduce the area overhead, a cluster-based approach is proposed, enabling scalability for larger hardware designs. The proposed mechanism is implemented on VEX VLIW processor. The obtained results show an average speed-up of 24.99% in performance with an almost 10% area and power overhead, when time scheduling is also considered on top of space scheduling. Compared to the unprotected version, the instruction reliability has increased by 2.2×.

Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs

In real-time rendering, a 3D scene is modelled with meshes of triangles that the GPU projects to the screen. They are discretized by sampling each triangle at regular space intervals to generate fragments which are then added texture and lighting effects by a shader program. Realistic scenes require detailed geometric models, complex shaders, high-resolution displays and high screen refreshing rates, which all come at a great compute time and energy cost. This cost is often dominated by the fragment shader, which runs for each sampled fragment. Conventional GPUs sample the triangles once per pixel; however, there are many screen regions containing low variation that produce identical fragments and could be sampled at lower than pixel-rate with no loss in quality. Additionally, as temporal frame coherence makes consecutive frames very similar, such variations are usually maintained from frame to frame. This work proposes Dynamic Sampling Rate (DSR), a novel hardware mechanism to reduce redundancy and improve the energy efficiency in graphics applications. DSR analyzes the spatial frequencies of the scene once it has been rendered. Then, it leverages the temporal coherence in consecutive frames to decide, for each region of the screen, the lowest sampling rate to employ in the next frame that maintains image quality. We evaluate the performance of a state-of-the-art mobile GPU architecture extended with DSR for a wide variety of applications. Experimental results show that DSR is able to remove most of the redundancy inherent in the color computations at fragment granularity, which brings average speedups of 1.68x and energy savings of 40%.

Evaluation of implementability in a malware detection mechanism using processor information

Currently, software implementation is the mainstream approach for anti-malware measures. However, software-based anti-malware measures are difficult to implement in Internet of Things devices with limited hardware resources. To solve this problem, a malware detection mechanism that can be realized with only hardware has been proposed. The hardware mechanism consists of three elements: an access-hit counter, dividers, and a classifier. The classifier is generated by a random forest and uses processor information as feature values. To reduce the hardware scale, a Hit Rate Table (HRTable) is introduced in place of the dividers. We propose methods of reducing the scale of hardware resources and synchronizing the CPU and the malware detection mechanism. This paper implements the proposed mechanism in hardware, simulates it while considering the delay caused by input/output to the HRTable, and evaluates the hardware scale of the proposed mechanism combined with RISC-V on a field-programmable gate array (FPGA).

On-the-Fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks

Many deep learning frameworks utilize GEneral Matrix Multiplication (GEMM)-based convolution to accelerate CNN execution. GEMM-based convolution provides faster convolution yet requires a data conversion process called lowering (i.e., im2col), which incurs significant memory overhead and diminishes performance. This paper proposes a novel hardware mechanism, called <i>On-the-fly Lowering Engine</i> (<i>OLE</i>), to eliminate the lowering overheads. Our goal is to offload the lowering overheads from the GEMM-based convolution. With OLE, the lowered matrix is neither pre-calculated nor stored in the main memory. Instead, a hardware engine generates lowered matrix on-the-fly from the original input matrix to reduce memory footprint and bandwidth requirements. Furthermore, the hardware offloading eliminates CPU cycles for lowering operation and overlaps computation with lowering to hide the performance overhead. Our evaluation shows that OLE can reduce memory footprint of convolutional layer inputs down to 1/12.5&#x00D7; and the overall memory footprint by up to 33.5%. Moreover, OLE can reduce the execution time of convolutional layers by 57.7% on average, resulting in an average speedup of 2.3&#x00D7; for representative CNN models.

DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path Profiler

Current state of the art application profilers for function/loop (process) based execution paths perform static profiling during design space exploration. Dynamic optimization is a must for heterogenous platforms to achieve low silicon area and better performance in real-time. Hence, it becomes necessary to have a mechanism in the target platform hardware to identify run-time characteristics of various processes of the application code in execution. This should be at both, an individual process level and in the relationship with other co-processes. This paper proposes DynPath - a hardware-based execution path profiler capable of detecting and identifying the processes along with the execution paths, both in a static and dynamic context. It has a rich set of features in comparison to other process-based profilers reported in the literature. Being non-intrusive it does not cause any run-time overheads. To handle the dynamic nature of input data size versus fixed memory row width, the paper proposes a unique approach based on Content Addressable Memory (CAM) for path identification and optimal hardware utilization. Considering that a process can be part of multiple executions paths, the profiler tracks both, the path invocation count, as well as, path-specific process invocation count (PSPIC) for each process. PSPIC logic being computationally intensive, it also proposes an alternative implementation of the PSPIC logic based on resource sharing which helps reduce the total area overhead of the execution path profiler by 87%.

Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency

Crossbar-based neuromorphic chips promise improved energy efficiency for spiking neural networks (SNNs), but suffer from the limited fan-in/fan-out constraints and resource mapping inefficiency. In this paper, we propose a new hardware mechanism to enable configurable combination of cores, called coreset. Using this hierarchical method, our end-to-end CSM (which stands for the ‘CoreSet Method’) framework efficiently solves the fan-in/fan-out issues and significantly improves the resource efficiency. Experiment results show that CSM can efficiently support complex network structures as well as significantly improving accuracies. Up to 4.6% improvement compared with those achieved by other neuromorphic chips (i.e. IBM TrueNorth and Intel Loihi), on the CIFAR-10, CIFAR-100 and SVHN datasets is achieved, matching the accuracies of state-of-the-art SNN models. In addition, compared with IBM TrueNorth, CSM achieves improvements of up to 18.5×,6.04× and 3.33× in memory efficiency, core efficiency and extrapolated throughput, respectively, thus enabling support for large-scale modern networks (such as VGG). In fact, our method can find optimal core sizes for minimal silicon area. As a proof of concept, we have implemented an FPGA emulation of coreset-supported neuromorphic computing. It achieves up to 7,737× speed-up compared to software simulation, thus not only facilitating SNN structure exploration and verification in a timely manner, but also enabling earlier prototyping for better neuromorphic hardware performance investigation.

TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling

Co-running GPU kernels on a single GPU can provide high system throughput and improve hardware utilization, but this raises concerns on application security. We reveal that translation lookaside buffer (TLB) attack, one of the common attacks on CPU, can happen on GPU when multiple GPU kernels co-run. We investigate conditions or principles under which a TLB attack can take effect, including the awareness of GPU TLB microarchitecture, being lightweight, and bypassing existing software and hardware mechanisms. This TLB-based attack can be leveraged to conduct Denial-of-Service (or Degradation-of-Service) attacks. Furthermore, we propose a solution to mitigate TLB attacks. In particular, based on the microarchitecture properties of GPU, we introduce a software-based system, TLB-pilot, that binds thread blocks of different kernels to different groups of streaming multiprocessors by considering hardware isolation of last-level TLBs and the application’s resource requirement. TLB-pilot employs lightweight online profiling to collect kernel information before kernel launches. By coordinating software- and hardware-based scheduling and employing a kernel splitting scheme to reduce load imbalance, TLB-pilot effectively mitigates TLB attacks. The result shows that when under TLB attack, TLB-pilot mitigates the attack and provides on average 56.2% and 60.6% improvement in average normalized turnaround times and overall system throughput, respectively, compared to the traditional Multi-Process Service based co-running solution. When under TLB attack, TLB-pilot also provides up to 47.3% and 64.3% improvement (41% and 42.9% on average) in average normalized turnaround times and overall system throughput, respectively, compared to a state-of-the-art co-running solution for efficiently scheduling of thread blocks.