Hardware IP Research Articles

Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP Against Piracy

Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP Against Piracy

Lightweight skin cancer detection IP hardware implementation using cycle expansion and optimal computation arrays methods

Skin cancer is recognized as one of the most perilous diseases globally. In the field of medical image classification, precise identification of early-stage skin lesions is imperative for accurate diagnosis. However, deploying these algorithms on low-cost devices and attaining high-efficiency operation with minimal energy consumption poses a formidable challenge due to their intricate computational demands. This study proposes a lightweight hardware design based on a convolutional neural network (CNN) for real-time processing of skin disease classifiers on portable devices. Our skin cancer recognition processor utilizes an optimally parallel designed processing engine (PE) for global computation, which greatly reduces hardware resource utilization by multiplexing of computational unit circuits. In addition, a design approach that provides loop unrolling effectively reduces the number of data accesses, thereby reducing computational complexity and logic resource requirements. The hardware circuits in this design perform data inference in convolutional, pooling, and fully connected layers based on 16-bit floating-point numbers. Evaluation of the HAM10000 database dataset shows that the architecture achieves an average classification accuracy of 97.8 %. We are the first to implement an all-hardware FPGA-based skin cancer detection platform that offers a 3.5x speedup in recognition compared to existing skin cancer accelerators at 50 MHz while consuming only 0.48 W of power. The implementation of this hardware architecture meets the major constraints of portable devices, featuring low resource utilization, low power consumption, and cost-effectiveness, while still providing efficient classification and high accuracy results.

The monitoring system of running state data of converter station equipment based on sensor information and 3D positioning algorithm

Abstract The stable operation of multiple equipment in the converter station can ensure the safety of the DC transmission system. Once the fault occurs, it will pose a threat to the safety and stability of the power grid. It is necessary to monitor the running state of all kinds of equipment, and study the monitoring system of the running state data of the converter station equipment based on sensor information and a three-dimensional positioning algorithm. In terms of hardware design, TCP and IP communication protocols are used to connect the sensors, and the sensors are arranged according to the vibration conduction standard, constituting a three-layer monitoring architecture of monitoring center, sensor, and equipment. The sensor module is connected by interface, and the structure of the connecting control board for sensor data transmission is set to increase the flexibility of sensor nodes. In software design, the basic information of converter station equipment is corresponding to sensor technology, and the database of operating equipment is established. A three-dimensional positioning algorithm is used to determine the data output form, detect the running state data of the converter station equipment, and complete the system design. The experiment takes various types of running data as the test object. Under the system application in this paper, different running data can be correctly classified and data monitoring under various states can be realized, which has application value.

Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection

Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm2, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.

GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security

GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security

M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs

M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs

Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework

Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

With the rapid development of technologies like artificial intelligence, high-performance computing chips are playing an increasingly vital role. The inverse hyperbolic sine and inverse hyperbolic cosine functions are of utmost importance in fields such as image blur and robot joint control. Therefore, there is an urgent need for research into high-precision, high-performance hardware Intellectual Property (IP) for arcsinh and arccosh functions. To address this issue, this paper introduces a novel 128-bit low-latency floating-point hardware IP for arcsinh and arccosh functions, employing an enhanced Coordinate Rotation Digital Computer (CORDIC) algorithm, achieving a computation precision of 113 bits in just 32 computation cycles. This significantly enhances computational efficiency while reducing hardware implementation latency. The results indicate that, when compared to Python standard results, the calculated error of the proposed hardware IP does not exceed 8×10−34. Furthermore, this paper synthesizes the completed IP using the TSMC 65 nm process, with a total IP area of 2.1056 mm2. Operating at a frequency of 300 MHz, its power is 22.4 mW. Finally, hardware implementation and resource analysis are conducted and compared on an Field Programmable Gate Array (FPGA). The results show that the improved algorithm trades a slight area increase for lower latency and higher accuracy. The designed hardware IP is expected to provide a more accurate and efficient computational tool for applications like image processing, thereby advancing technological development.

HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learning

AbstractLinear Regression (LR), as one of the essential Machine Learning (ML) models, incurs massive data crunching during the training phase based on many data points. Considering the computationally intensive nature in the LR models, an optimized dedicated hardware IP core design can be very effective. This paper proposes the following novelties: (a) an optimized hardware IP core design of linear regression‐based machine learning model using high‐level synthesis (HLS). More specifically, independent application specific datapath architectures of hardware IP for computing optimal bias and intercepts and cost function in LR‐ML are presented here; (b) an optimized hardware IP core design of LR based ML model by deducing dependency graph from its corresponding mathematical foundation; (c) register transfer level (RTL) design, using HLS, of the optimized LR based ML hardware IP core for computing cost function; (d) linear regression IP core design using multi‐layered tree‐height transformation (THT) and swarm intelligence based architectural exploration for optimized HLS design.

Hardware IP Assurance against Trojan Attacks with Machine Learning and Post-processing

System-on-chip (SoC) developers increasingly rely on pre-verified hardware intellectual property (IP) blocks often acquired from untrusted third-party vendors. These IPs might contain hidden malicious functionalities or hardware Trojans that may compromise the security of the fabricated SoCs. Lack of golden or reference models and vast possible Trojan attack space form some of the major barriers in detecting hardware Trojans in these third-party IP (3PIP) blocks. Recently, supervised machine learning (ML) techniques have shown promising capability in identifying nets of potential Trojans in 3PIPs without the need for golden models. However, they bring several major challenges. First, they do not guide us to an optimal choice of features that reliably covers diverse classes of Trojans. Second, they require multiple Trojan-free/trusted designs to insert known Trojans and generate a trained model. Even if a set of trusted designs are available for training, the suspect IP can have an inherently very different structure from the set of trusted designs, which may negatively impact the verification outcome. Third, these techniques only identify a set of suspect Trojan nets that require manual intervention to understand the potential threat. In this article, we present VIPR, a systematic machine learning (ML)-based trust verification solution for 3PIPs that eliminates the need for trusted designs for training. We present a comprehensive framework, associated algorithms, and a tool flow for obtaining an optimal set of features, training a targeted machine learning model, detecting suspect nets, and identifying Trojan circuitry from the suspect nets. We evaluate the framework on several Trust-Hub Trojan benchmarks and provide a comparative analysis of detection performance across different trained models, selection of features, and post-processing techniques. We demonstrate promising Trojan detection accuracy for VIPR with up to 92.85% reduction in false positives by the proposed post-processing algorithm.

Hardware Design and Implementation of a Lightweight Saber Algorithm Based on DRC Method

With the development of quantum computers, the security of classical cryptosystems is seriously threatened, and the Saber algorithm has become one of the potential candidates for post-quantum cryptosystems (PQCs). To address the problems of long delay and the high power consumption of Saber algorithm hardware implementation, a lightweight Saber algorithm hardware design scheme based on the joint optimization of data readout and clock (DRC) was proposed. Firstly, an analysis was carried out on the hardware architecture, timing overhead and power consumption distribution of the Saber algorithm, and the key circuits that limit the performance of the algorithm were identified; secondly, a dual-port SRAM parallel reading method was adopted to improve the data reading efficiency and reduce the timing overhead of double data reading in the multiplier module. Then, a clock gating technology was used to reduce the dynamic flipping probability of internal registers and reduce the hardware power consumption of the Saber algorithm; finally, data reading and clock gating were jointly optimized to design a high-speed and low-power Saber algorithm hardware IP core. Lightweight IP cores were integrated into RISC-V SoC systems via APB bus in a TSMC 65 nm process to complete the digital back-end design. The experimental results show an IP core area of 0.99 mm2 and power consumption of 8.49 mW, which is 33% lower than that reported in the related literature. Under 72 MHz & 1 V operating conditions, the number of clock cycles for the Saber algorithm’s key generation, encryption and decryption are 3315, 9204 and 1420, respectively.

Convolutional neural network-based lightweight hardware IP core design for EEG epilepsy prediction

Epilepsy is one of the most common neurological disorders. In order to realize a portable and wearable epilepsy prediction device, a lightweight hardware IP core is proposed for EEG epilepsy prediction. The scheme first analyzes the epileptic EEG signal and extracts the time-frequency feature maps of interictal and preictal EEG signals. Then it reduces the network parameters using the single-channel approach to reduce the number of neurons and network complexity, and trains the lightweight epilepsy prediction convolutional neural network by combining the time-frequency feature maps. Finally, a hardware convolutional layer is designed with pipeline function, and it connect 8 layers with feature map buffer to realizes the lightweight EEG epilepsy prediction hardware IP core. Using TSMC 65 nm process, the hardware IP core is functionally verified with 87.9% prediction accuracy. The area is 2.55 mm2 and the power is 4.45 mW. Under 1V & 20 MHz operating conditions, single prediction latency is 3.29 ms and energy efficiency is 0.146 μJ/class.

Field programmable gate array based moving object tracking system for robot navigation

This paper proposes a method in which an object tracking robot system is implemented on field programmable gate arrays (FPGAs). The OV7670 camera provides real-time object pictures to the system. To improve picture quality, images are put via the median filter phase. The item is distinguished from the backdrop based on color (red), after which it is subjected to a mathematical morphological approach of filtering to eliminate noise. To send the robot control signals, the object's (new) coordinates are found. In this method, the median filter, color separation, hardware IP cores, and morphological filter are all part of the embedded system on FPGA. Through the direct memory access (DMA) controller, these cores may communicate and perform high-speed pipeline computing at higher data rates. The entire system is executed in real-time on Xilinx's spartan-6 FPGA KIT. The results show practical and promise.

Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA

Wearable devices used for personal monitoring applications have been improved over the last decades. However, these devices are limited in terms of size, processing capability and power consumption. This paper proposes an efficient hardware/software embedded system for monitoring bio-signals in real time, including a heart rate calculator using PPG and an emotion classifier from EEG. The system is suitable for outpatient clinic applications requiring data transfers to external medical staff. The proposed solution contributes with an effective alternative to the traditional approach of processing bio-signals offline by proposing a SoC-FPGA based system that is able to fully process the signals locally at the node. Two sub-systems were developed targeting a Zynq 7010 device and integrating custom hardware IP cores that accelerate the processing of the most complex tasks. The PPG sub-system implements an autocorrelation peak detection algorithm to calculate heart rate values. The EEG sub-system consists of a KNN emotion classifier of preprocessed EEG features. This work overcomes the processing limitations of microcontrollers and general-purpose units, presenting a scalable and autonomous wearable solution with high processing capability and real-time response.

Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks

To satisfy various design requirements and application needs, designers integrate multiple intellectual property blocks (IPs) to produce a system on chip (SoC). For improved survivability, designers should be able to patch the SoC to mitigate potential security issues arising from hardware IPs; for increased flexibility, we propose adding programmable hardware-based support for monitoring and bug mitigation. However, it is a challenge to decide how much additional cost a designer should expend up front to deal with unknown, future issues. We propose an approach that guides designers toward maximizing the benefits of adding “patchability” to various IPs in the system, given a target resource overhead. We frame the design problem as an integer quadratic program and show that our approach achieves superior patchability compared to the naïve and baseline approaches for a given cost limit. Experimental results show that when we set a cost limit of 2% field-programmable gate array adaptive logic module usage, our solution can generate a viable patching infrastructure with six patching blocks offering patches for seven different services in our case study.

WAYS OF THE ASTERISK SOFTWARE PBX PROTECTION

Network protection of the Asterisk software PBX widely used in modern info-communication networks is considered. This particular telephone exchange is used to set up telephone communications at the Moscow Technical University of Communications and Informatics. When connecting this software telephone exchange to IP networks, it is necessary to provide its protection to prevent it from being attacked by intruders. The Asterisk IP PBX has powerful protection tools. If properly applied, they can make the protection more reliable than that of some hardware IP PBXs. The protection system can be built in different ways. The most popular ones are the following types of protection: the iptables utility, the development of a proper network design involving the use of VLAN and VPN technologies, the utilization of Fail2Ban log file analyzer. Protection can also be implemented by means of DialPlan and developing a proper configuration of the Asterisk IP PBX.

Customizable FPGA-Based Hardware Accelerator for Standard Convolution Processes Empowered with Quantization Applied to LiDAR Data.

In recent years there has been an increase in the number of research and developments in deep learning solutions for object detection applied to driverless vehicles. This application benefited from the growing trend felt in innovative perception solutions, such as LiDAR sensors. Currently, this is the preferred device to accomplish those tasks in autonomous vehicles. There is a broad variety of research works on models based on point clouds, standing out for being efficient and robust in their intended tasks, but they are also characterized by requiring point cloud processing times greater than the minimum required, given the risky nature of the application. This research work aims to provide a design and implementation of a hardware IP optimized for computing convolutions, rectified linear unit (ReLU), padding, and max pooling. This engine was designed to enable the configuration of features such as varying the size of the feature map, filter size, stride, number of inputs, number of filters, and the number of hardware resources required for a specific convolution. Performance results show that by resorting to parallelism and quantization approach, the proposed solution could reduce the amount of logical FPGA resources by 40 to 50%, enhancing the processing time by 50% while maintaining the deep learning operation accuracy.

Design of Hardware IP Core Security Protection Based on Multi-Level Co-obfuscation

Most of the reported hardware obfuscations are single-level ones focusing on physical level, logical level or behavior level, in which the lack of synergy among different levels commonly results in limited security performance. Based on study of the relationships among circuit layout, logic and states transition, a multi-level co-obfuscation scheme is proposed to protect hardware IP cores. In bottom-up collaborative confusion design, dummy vias are introduced into camouflage gates layout to perform physical-logic obfuscation, and via-PUF (Physical Unclonable Fuction) are utilized in state transition control to realize physical-behavior obfuscation. Then, in top-down collaborative obfuscation design, logic locks are used to perform behavior-logic obfuscation, and parallel-branch obfuscation wire technique is designed to complete the behavior-physical confusion. Finally, a substitution algorithm of the obfuscation gates into the circuit’s netlist is proposed, and the three-level cooperative obfuscation is realized to achieve IP core security protection. ISCAS-89 Benchmarks and a typical cryptogram algorithm are used to verify the correctness and efficiency of the proposed IP core protection scheme. The test results show that under TSMC 65nm process, the average area cost percentage of the proposed co-obfuscation in large-scale circuits is 11.7%, the average power consumption accounts for 5.1%, The difference of register toggle between correct and wrong keys is less than 10%, and the proposed scheme can effectively resist violence attack, reverse engineering, boolean SATisfiability (SAT) attack.

Estimating the Memory Consumption of a Hardware IP Defragmentation Block

IP fragmentation is still prevalent on the Internet. Defragmented traffic is a prerequisite for many network processing algorithms. This work focuses on the size and organization of a flow table, which is an essential ingredient of the hardware IP defragmentation block. Previous research suggests that fragmented IP traffic is highly local, and a relatively small flow table (on the order of a thousand entries) can process most of the traffic. Samples of IP traffic were obtained from public data sources and used for a statistical analysis, revealing the key factors in achieving design goals. The findings were backed by an extensive design space exploration of the software defragmentation model, which resulted in the efficiency estimates. To provide a robust score of the simulation model, a new validation technique is employed that helps to overcome the limitations of the samples.