Real-time Processing Hardware Research Articles

LAMANet: A Real-Time, Machine Learning-Enhanced Approximate Message Passing Detector for Massive MIMO

Model-driven machine learning for signal detection in the physical layer of mobile communication systems combines well-known detector structures with learned parameters. Recent work has shown high detection performance in massive multiple-input–multiple-output (MIMO) detection; however, thorough complexity analysis and real-time processing hardware are lacking. This work proposes a novel machine learning enhanced approximate message passing (AMP) algorithm named LAMANet and its hardware implementation. The algorithm solves some major challenges of previous proposals such as the complete loss of performance in untrained detectors and the still high computational complexity compared to traditional massive MIMO detection methods. We provide a comprehensive complexity comparison, simulations of the symbol error rate (SER) performance over realistic channel models, and a field-programmable gate array (FPGA) implementation capable of processing LAMANet in real time. The results show a similar detection performance of LAMANet to previous machine learning-enhanced algorithms, while the computational effort is reduced to a level where real-time computation in hardware becomes comparable to traditional detection methods.

Hardware-friendly architecture for a pseudo 2D weighted median filter based on sparse-window approach

Stereo matching, which is conventionally used for three-dimensional (3D) information acquisition through cameras, is the most actively studied subject in computer vision. To obtain sophisticated 3D information, refining the disparity map in stereo vision is important. The weighted median filter (WMF) is extensively used to eliminate outliers in post-processing. To this end, various studies have implemented WMFs in hardware for real-time processing. Among them, the separable weighted median filter (sWMF) vertically and horizontally separates a two-dimensional WMF into two one-dimensional WMFs to reduce hardware resource usage. Herein, we propose a hardware architecture that can reduce the hardware resource usage of the sWMF by applying the sparse-window approach, which is a method of creating a window by selecting pixels sparsely. This approach makes it possible to reduce drastically the number of elements to be computed. Although the proposed architecture has an insignificant disparity error rate, similar to that of the sWMF, it saves 33% slice lookup tables (LUTs) and 69% slice registers when using a window size of 37 × 37 pixels as the synthesis result on the Xilinx XC7K325T FPGA. When a window size of 49 × 13 pixels with the best performance is used, the proposed architecture uses 7335 slice LUTs, 4126 slice registers, and 21 block RAMs. The proposed architecture operates at frequencies of up to 167.95 MHz; hence, it can operate in real time. The proposed WMF architecture is suitable for application in embedded systems and low-resource environments as it is hardware-friendly.

Multivariable control of a test bed for differential gears

Common problems related to the control of power train test beds are the coupling of the two typical controlled variables rotational speed and testing torque as well as resonant torque oscillations. This work presents a simplified non-linear mathematical model of a test bed for differential gears including the unit under test suitable for controller design. Based on this system model, a new control concept with input–output decoupling and feedback linearisation is developed to overcome both previously mentioned problems. Simulation studies using the proposed control structure as well as a conventional control concept for power train test beds show the superiority of the new controller.Finally the proposed controller was implemented on real-time processing hardware and tested on a commercial test bed for differential gears to prove the performance of the new control concept in practice.

An Efficient and Automatic Systolic Peak Detection Algorithm for Photoplethysmographic Signals

of physiological signals often involves detection of peaks and finding intervals between them. Well developed methods are available for Electrocardiogram(ECG) QRS complex detection. However, there are only a few algorithms published for peak detection suitable for pulse wave signals such as arterial pressure wave and photoplethysmographic (PPG) signals. Algorithms for detection of QRS complex in ECG are based on the impulsive character of the signal and are not applicable for pulse wave signals, which are more sinusoidal in nature and the shape varies with age. In this background, a versatile algorithm based on the physiology of the pulse wave is developed to detect the peaks from a pulse wave signal such as PPG. The algorithm combines the technique of moving average of valley-peak differences with an adaptive threshold filtering to detect the systolic peaks. The algorithm is validated against a publicly available validation dataset and achieved a sensitivity of 99.82 and a positive predictivity of 98.88 when compared to expert manual annotations. This algorithm is computationally simple and can be easily implemented in real time processing hardware.

一种基于DSP+CPLD的低功耗实时红外成像系统实现方法

The inherent nonuniformity of the uncooled infrared focal plane arrays(IRFPA) crucially limits its imaging quality,and there is also a contradiction between the wide dynamic range of infrared source and the small of it for display.To solve these problems,the embedded infrared image real-time processing hardware system is designed which adopts a complex programmable logic device(CPLD) to drive the timing sequence of IRFPA and video encoder,with a core of high-speed and low power consumption digital signal processor(DSP).Combination with two-point correction,a segmentation gray scale compressing transform method based on histogram statistics threshold is proposed and experimented.The results prove that the image can be captured and processed real-timely,the processed image is corrected effectively,and the background is suppressed while the target and details are enhanced.The proposed scheme with simple architecture,high reliability and low power consumption characters can provide a valuable reference for the development of miniaturized thermal infrared imager.

Filtering and Rendering of Resolution-Dependent Reflectance Models

The reflectance of a surface depends upon the resolution at which it is imaged. In this work, we propose to represent this resolution-dependent reflectance as a mixture of multiple conventional reflectance models and present a framework for efficiently rendering the reflectance effects of such mixture models over different resolutions. To rapidly determine reflectance at runtime with respect to resolution, we record the mixture model parameters at multiple resolution levels in mipmapss and propose a technique to minimize aliasing in the filtering of this mipmaps. This framework can be applied to several widely used parametric reflectance models and can be implemented in graphics hardware for real-time processing, using a presented hardware-accelerated technique for nonlinear filtering of mixture model parameters. In addition, shadowing and masking effects can be included into this framework to increase the realism of rendering. With this mixture model filtering and rendering framework, our system can efficiently render the fine reflectance detail that is customarily disregarded in conventional rendering methods.

Generic Hardware Architectures for Sampling and Resampling in Particle Filters

Particle filtering is a statistical signal processing methodology that has recently gained popularity in solving several problems in signal processing and communications. Particle filters (PFs) have been shown to outperform traditional filters in important practical scenarios. However their computational complexity and lack of dedicated hardware for real-time processing have adversely affected their use in real-time applications. In this paper, we present generic architectures for the implementation of the most commonly used PF, namely, the sampling importance resampling filter (SIRF). These provide a generic framework for the hardware realization of the SIRF applied to any model. The proposed architectures significantly reduce the memory requirement of the filter in hardware as compared to a straightforward implementation based on the traditional algorithm. We propose two architectures each based on a different resampling mechanism. Further, modifications of these architectures for acceleration of resampling process are presented. We evaluate these schemes based on resource usage and latency. The platform used for the evaluations is the Xilinx Virtex II pro FPGA. The architectures presented here have led to the development of the first hardware (FPGA) prototype for the particle filter applied to the bearings-only tracking problem.