Hardware Efficient Finite Impulse Response Research Articles

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

Hardware efficient FIR filter design using Global Best Steered Quantum Inspired Cuckoo Search Algorithm

In this paper, a new algorithm namely Global Best Steered Quantum Inspired Cuckoo Search Algorithm (GQICSA) is proposed for obtaining optimized set of coefficients to implement Finite Impulse Response (FIR) Filter. Adder cost of a filter is estimated after quantizing the filter coefficients followed by Common Sub-expression Elimination (CSE). We found from the simulation results that reduction in word length of coefficients does not make the filters fail to achieve the ideal frequency response. Moreover, filters developed using GQICSA outperform the benchmark filters designed by Parks McClellan Algorithm in terms of stopband attenuation. Analysis of the results reveal that GQICSA not only improves over various conventional algorithms including Cuckoo Search Algorithm (CSA), it also surpasses modified version of CSA, Quantum Inspired CSA (QICSA) updated using quantum principles, for optimizing filter coefficients to design lower hardware costing filter without compromising the filter responses and efficiency. GQICSA also provides significant improvements compared to CSA and QICSA in terms of stopband attenuation and execution time for higher order filter design. Efficiency of GQICSA over QICSA and conventional CSA is also proved with 16 benchmark functions.

An approach for FIR filter coefficient optimization using differential evolution algorithm

In this paper, we present a hardware efficient finite impulse response (FIR) filter design using differential evolution (DE) and common sub expression (CSE) elimination algorithm. With the DE algorithm, we first found a set of filter coefficients with reduced number of signed-power-of-two (SPT) terms without compromising on quality of the filter response. After obtaining coefficients, we applied CSE elimination algorithm, and determined the hardware cost in terms of adders. The filters were designed using DE for various word lengths, and the same were implemented in transposed direct form (TDF) structure. The implemented filters were synthesized in Cadence RTL compiler using UMC 90nm technology. We compared the performances of our filters with recently best published works in terms of area, delay, power and power-delay-product (PDP). One of the proposed filters found to improve a PDP gain of 29% compared to Remez algorithm. The proposed approach showed improvements in filter design for the given specifications.

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.