Hardware Description Language Programming Research Articles

Studying the challenges of developing hardware description language programs

Studying the challenges of developing hardware description language programs

Mighty Macros and Powerful Parameters: Maximizing Efficiency and Flexibility in HDL Programming

This paper explores the use of macros and parameters in Hardware Description Language (HDL) programming. Macros and parameters are powerful tools that allow for efficient and reusable code, yet their full potential is often underutilized. By examining the advantages of macros and parameters, this paper aims to demonstrate how these features can enhance the flexibility, readability, and maintainability of HDL code. Additionally, the paper discusses the use cases of mixing macros and parameters in HDL programming, highlighting their applicability in a range of scenarios. Furthermore, the paper addresses the challenges that arise from the mix use of macros and parameters and provides best practices to overcome these challenges. Overall, this paper aims to encourage HDL programmers to fully explore the capabilities of macros and parameters in their code, leading to more efficient and effective hardware designs and verification.

Automatic diseases detection and classification of EEG signal with pervasive computing using machine learning

PurposeThe natural control, feedback, stimuli and protection of these subsequent principles founded this project. Via properly conducted experiments, a multilayer computer rehabilitation system was created that integrated natural interaction assisted by electroencephalogram (EEG), which enabled the movements in the virtual environment and real wheelchair. For blind wheelchair operator patients, this paper involved of expounding the proper methodology. For educating the value of life and independence of blind wheelchair users, outcomes have proven that virtual reality (VR) with EEG signals has that potential.Design/methodology/approachIndividuals face numerous challenges with many disorders, particularly when multiple dysfunctions are diagnosed and especially for visually effected wheelchair users. This scenario, in reality, creates in a degree of incapacity on the part of the wheelchair user in terms of performing simple activities. Based on their specific medical needs, confined patients are treated in a modified method. Independent navigation is secured for individuals with vision and motor disabilities. There is a necessity for communication which justifies the use of VR in this navigation situation. For the effective integration of locomotion besides, it must be under natural guidance. EEG, which uses random brain impulses, has made significant progress in the field of health. The custom of an automated audio announcement system modified to have the help of VR and EEG for the training of locomotion and individualized interaction of wheelchair users with visual disability is demonstrated in this study through an experiment. Enabling the patients who were otherwise deemed incapacitated to participate in social activities, as the aim was to have efficient connections.FindingsTo protect their life straightaway and to report all these disputes, the military system should have high speed, more precise portable prototype device for nursing the soldier health, recognition of solider location and report about health sharing system to the concerned system. Field programmable gate array (FPGA)-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centered on EEG signals, the soldier’s health is observed on systematic bases. By emerging Verilog hardware description language (HDL) programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t the whole work is approved in a Vivado Design Suite. Classification of different abnormalities and cloud storage of EEG along with the type of abnormalities, artifact elimination, abnormalities identification based on feature extraction, exist in the segment of suggested architecture. Irregularity circumstances are noticed through developed prototype system and alert the physically challenged (PHC) individual via an audio announcement. An actual method for eradicating motion artifacts from EEG signals that have anomalies in the PHC person’s brain has been established, and the established system is a portable device that can deliver differences in brain signal variation intensity. Primarily the EEG signals can be taken and the undesirable artifact can be detached, later structures can be mined by discrete wavelet transform these are the two stages through which artifact deletion can be completed. The anomalies in signal can be noticed and recognized by using machine learning algorithms known as multirate support vector machine classifiers when the features have been extracted using a combination of hidden Markov model (HMM) and Gaussian mixture model (GMM). Intended for capable declaration about action taken by a blind person, these result signals are protected in storage devices and conveyed to the controller. Pretending daily motion schedules allows the pretentious EEG signals to be caught. Aimed at the validation of planned system, the database can be used and continued with numerous recorded signals of EEG. The projected strategy executes better in terms of re-storing theta, delta, alpha and beta complexes of the original EEG with less alteration and a higher signal to noise ratio (SNR) value of the EEG signal, which illustrates in the quantitative analysis. The projected method used Verilog HDL and MATLAB software for both formation and authorization of results to yield improved results. Since from the achieved results, it is initiated that 32% enhancement in SNR, 14% in mean squared error (MSE) and 65% enhancement in recognition of anomalies, hence design is effectively certified and proved for standard EEG signals data sets on FPGA.Originality/valueThe proposed system can be used in military applications as it is high speed and excellent precise in terms of identification of abnormality, the developed system is portable and very precise. FPGA-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centered on EEG signals the soldier health is observed in systematic bases. The proposed system is developed using Verilog HDL programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t and synthesised using in Vivado Design Suite software tool.

FPGA-based experiments for demonstrating bi-stability in tabu learning neuron model

PurposeThe purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model.Design/methodology/approachNumerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board.FindingsWith the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit.Originality/valueWithout any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.

A Multiscroll Chaotic Attractors with Arrangement of Saddle-Shapes and Its Field Programmable Gate Array (FPGA) Implementation

Based on the step function and signum function, a chaotic system which can generate multiscroll chaotic attractors with arrangement of saddle-shapes is proposed and the stability of its equilibrium points is analyzed. The under mechanism for the generation of multiscroll chaotic attractors and the reason for the arrangement of saddle shapes and being symmetric abouty-axis are presented, and the rule for controlling the number of scroll chaotic attractors with saddle shapes is designed. Based on the core chips including Altera Cyclone IV EP4CE10F17C8 Field Programmable Gate Array and Digital to Analog Converter chip AD9767, the peripheral circuit and the Verilog Hardware Description Language program for realization of the proposed multiscroll chaotic system is constructed and some experimental results are presented for confirmation. The research result shows that the occupation of multipliers and Phase-Locked Loops in Field Programmable Gate Array is zero.

Fast simulation of an RF-MEMS toggle-switch through a behavioural models software library of elementary components

Simulation of MEMS-based, microelectromechanical-systems, radio frequency (RF) passive components, i.e. RF-MEMS, is not an easy task, as it involves the coupling of different physical domains (mechanical, electrical, electromagnetic). This work discusses the exploitation of a software library of elementary MEMS behavioural models, in order to predict the multi-physical behaviour of a complex RF-MEMS switch geometry, i.e. a toggle-switch. The elementary models developed and available in the software library are implemented in an HDL (hardware description language) programming code and can therefore be exploited within standard development environments for integrated circuits.

Innovative and rapid design for I2C (inter-integrated circuit) interface communication of FPGA chips

A new design flow is proposed to greatly improve the efficiency and accuracy of the HDL program design. This paper successfully completes the FPGA (Field-Programmable Gate Array) chip’s external communication I2C interface design of new design flow not traditionally one. FPGA chip is often used in mobile phones, military, aerospace or other industries. Even INTEL and Microsoft and other large companies have begun to acquire FPGA-related companies, showing its importance. But the FPGA language is written in the Hardware Description Language (HDL) which is a mechanical engineering staff obstacles. Therefore, this article makes use of the MATLAB / SIMULINK tool, which is familiar with the engineering staff, to complete the FPGA chip’s I2C interface design. The advantage is that the functional simulation and HDL program can be completed at the same time, do not have to perform the function after the simulation before designing HDL program. The traditional design wastes many times to revise back and forth between function simulation and HDL program design. Finally an experimental illustration is proposed to verify the proposed design of the I2C communication interface for an HDL program on the read and write experiments of Electrically-Erasable Programmable Read-Only Memory (EEPROM).

OpenCL Implementation of FPGA-Based Signal Generation and Measurement

Signal generation and measurement have been widely used in many engineering applications, such as for creating test signals in radar, communication, and software-defined radio. In field programmable gate array (FPGA) design, to generate and measure an analog signal, compatible software and hardware interfaces are required. Traditionally, hardware description language (HDL) is required to program an FPGA. HDL programming provides an efficient logic resource with low latency. However, it is time-consuming for designs that are more complex. Currently, OpenCL is implemented for FPGA programming. OpenCL reduces the FPGA development time because it increases the abstraction level of the code. OpenCL is an open and royalty-free framework for accelerating the algorithm executed on a heterogeneous system, such as a GPU, CPU, DSP, or FPGA. OpenCL implementation on FPGAs yields high-performance results for the computation process. However, compared to HDL design, OpenCL does not provide a particular function to access the FPGA hardware directly. In this paper, we have demonstrated the implementation of OpenCL programming on an FPGA for signal generation and measurement. We have developed OpenCL components that can interact with the FPGA hardware directly. An OpenCL I/O channel extension is employed in the kernel to read data from and write data to the OpenCL components. The experimental results indicate that OpenCL can be used for signal measurement and generation using FPGAs.

A simple digital control system with field-programmable gate array for stabilization of CO2 laser output.

A simple digital control system was designed to stabilize CO2 laser based on digital signal processing with the Field-Programmable Gate Array (FPGA) controlling chip and Very-High-Speed Integrated Circuit Hardware Description Language program. In this system, the control parameters were easily determined by software real-time control, and the control circuit was also designed compactly. In addition, the theoretical analysis on the stabilization of CO2 laser output characteristics was presented based on the photoacoustic effect, and the corresponding experiments on the stabilization of CO2 laser output characteristics were further performed. The results show that the output power of CO2 laser is stabilized at the peak with a relative power stability of 2.71%. Furthermore, the frequency of CO2 laser 9P(36) line is stabilized at the center of the laser gain curve with a relative stability of (1.57 ± 0.37)×10-8. This system has a potential of further improvements by optimizing the algorithm and choosing higher-speed signal processor.

Design of Phase Shift Signal Generator

A phase shift signal generator which has high precision and whose phase can be easily and digitally controlled is designed through utilizing DDS technology. A method which can replace complicated hardware description language programming through calling modules and setting parameters is proposed. The designed phase shift signal generator passes waveform simulation under Simulink and SignalTap Ⅱcertification, and the results obtained on the FPGA board are correct. The DSP Builder is utilized to design the phase shift signal generator, which reduces the difficulty of the design and shortens the design time.

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

Programmable logic controller (PLC) is one of the most important components in today’s manufacturing. Its performance-based microprocessor and software have been a bottleneck for improving its efficiency. To enhance the PLC performance and flexibility, a new PLC design based on field programmable gate array (FPGA) has been a hot topic because of its parallel execution mechanism and reconfigurable hardware structure. From practical viewpoint, in this paper, the authors propose an approach to implement the existing ladder diagram (LD) inside FPGA making full use of the advantage of FPGA device. The essential of this research includes two issues: (a) analyze the LD program and organize it with sequential and parallel structure and (b) implement the sequential and parallel structure of the LD program with hardware description language inside FPGA. To the first work, the condensed simultaneity graph theory is applied to optimize the LD program with sequential and parallel structure. To the second work, Boolean equations are taken as the bridge to convert the optimized LD program to the hardware description language program. Finite state machine is used to generate sensitive signals to guarantee that the performance of the converted very high-speed integrated circuit hardware description language design is the same as the original ladder diagram. A case study is practiced to verify the proposed approach in this paper.

Study on LD-VHDL conversion for FPGA-based PLC implementation

Programmable logic controllers (PLCs) have been widely used in manufacturing systems for many years. PLC performance is highly constrained by speed of the microprocessor and real-time firmware of the PLC. To enhance conventional PLC performance and flexibility, this paper proposes a new PLC design based on field programmable gate array (FPGA) with parallel execution mechanism and reconfigurable hardware structure. Since ladder diagrams (LD) are the most popular programming language of PLCs, the essential approach of this research is to convert LD programs to equivalent and very high speed integrated circuit hardware description language programs (VHDL), which are the major programming language for FPGA design. This conversion process requires two steps. The first step is to convert the LD program to a VHDL program, in which the LD sequence is controlled by a state machine process. The second step is to optimize the state machine process with concurrent sensitive signals to assure that independent operations in the LD program can be executed in parallel in FPGA. Considering the diversity of LD instructions from different PLC providers, a universal converter with an extended Boolean equation as a bridge is introduced to implement the conversion of LD programs to VHDL. In the second step, the condensed simultaneity graph theory (CSG) is applied to optimize the converted VHDL program with concurrent sensitive signals, which is explained by a practical example.

Constraint-based watermarking techniques for design IP protection

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.