Hardware Description Language Description Research Articles

An integrated machine code monitor for a RISC-V processor on an FPGA

This paper proposes an integrated machine code monitor (iMCM) written in a hardware description language (HDL) and implemented in an FPGA together with a processor. The iMCM reconfigures monitor functions to be provided according to the verification progress of the processor design and the development situation of basic programs. The iMCM was implemented in the FPGA together with the processor as hardware synthesized from HDL description for requested iMCM functions. The iMCM was implemented its functions based on survey questionnaire result for six developers of some processors in FPGAs. And, its correct operation was confirmed by simulation and evaluation using FPGA devices. RISC-V was adopted as an ISA of the target processor. A subset composed of 27 instructions of the compression type instruction set extension with 16-bit instruction word length among RISC-V was employed. All state machines and sequential processes were written in Verilog HDL and implemented together with the processor core as a single circuit by circuit synthesis, placement, and routing. A 41% LUT was added to the implementation of the iMCM against the simple processor implementation. This addition depends on the monitor function to be selected and reconfigured. Furthermore, the iMCM programmed in the FPGA was confirmed to operate at 100 MHz with the circuit mounted on an FPGA evaluation board.

HDL Constructs in Linear Word-Level Decision Diagram Based Specification

Linear Decision Diagrams (LDDs) are used in the paper as an intermediate format that allows us to quickly generate the circuit netlist from HDL (hardware description language), such as Verilog, or transform it to HDL description for further ASIC or FPGA synthesis and verification. The results of an extensive experimental study (on memory requirements, run time to convert LDD intermediate format to/from HDL, and verification via simulation) are reported here.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

HDL presynthesis optimizations using a tabular model

In this paper, we introduce presynthesis optimizations on hardware description languages (HDLs). Presynthesis optimizations consist of two categories of tasks: 1) source-level transformations, which produce optimized behavioral HDL descriptions that lead to improved synthesis results and 2) source-level analysis, which produces information useful in the synthesis stage to improve the quality of the synthesized circuits. Presynthesis optimizations are carried out on an intermediate tabular representation called timed decision table (TDT). We have implemented the TDT-based presynthesis optimization algorithms in a software package called Pumpkin. Experiments running Pumpkin on named benchmarks show promising results.

Automatic verification of implementations of large circuits against HDL specifications

This paper addresses the problem of verifying the correctness of gate-level implementations of large synchronous sequential circuits with respect to their higher level specifications in a hardware description language (HDL). The verification strategy is to verify containment of the finite state machine (FSM) represented by the HDL description in the gate-level FSM by computing pairs of compatible states. This formulation of the verification problem dissociates the verification process from the specification of initial states, whose encoding may be unknown or obscured during optimization and also enables verification of reset circuitry. To make verification of large circuits with merged data path and control tractable, the concept of strong containment is introduced. This is a conservative approach which exploits correspondence between data path-registers in the two descriptions without requiring any correspondence between the control units. We also present an important result and associated proof that computation of pairs of equivalent or compatible states can be achieved by considering subsets of the circuit outputs. Consequently, verification of circuits with large and diverse input-output sets, which was previously intractable due to lack of a single effective variable order for the binary decision diagrams (BDD's), is now feasible. Experimental results are presented for the verification of several industry level circuits.

Design and implementation of synthesis prediction in RTL design

AbstractConsideration is given to predicting the realizability of the logic synthesis and the circuit scale after the logic synthesis at the stage of the functional design before the logic synthesis. If this is realized, the manual re‐design part, as well as the execution time for logic synthesis can greatly be reduced, which is a problem at the present logic synthesis.This paper considers the stage of HDL description (functional description) at the register transfer level (RTL) before the logic synthesis based on the hardware description language (HDL). It presents a method of synthesis prediction, which can predict the realizability of the logic circuit expected after the logic synthesis. In the proposed synthesis prediction, the expertise of the HDL description for the logic synthesis integrated into the knowledge in the database and the following functions are provided.The synthesis possibility function determines the realizability of the logic synthesis using the constructed synthesis template. The guidance function transforms interactively the HDL description, for which the logic synthesis is decided as unrealizable, into the logic synthesis description for which the logic synthesis is possible. The predictive estimation function estimates the circuit scale (in terms of the number of logic gates) after the logic synthesis.The proposed synthesis prediction methodology is applied to the HDL macrogeneration system. It is seen that the logic circuit as intended by the designer is obtained by the logic synthesis, and the predicted number of logic gates agreed with that of the circuit after the logic synthesis within ± 10 percent, in terms of the median value. The proposed synthesis prediction can be executed with more than 100 times higher speed compared to the actual logic synthesis execution time.

Comparing layouts with HDL models: a formal verification technique

This paper discusses a formal verification technique for comparing the functionality of a transistor netlist extracted from a layout with a design description in a hardware description language (HDL). Using novel techniques based on binary decision diagrams (BDD's), a state machine is first abstracted from a transistor netlist, given information relating to clock signals and clock models. The resulting state machine behavior is then compared with another that is derived from the HDL description. The basic ingredients of the technique used can be directly applied (or, in other cases, extended) to various related contexts of interest. In particular, the abstracted machine(s) can be represented as BDD relations or as synchronous sequential networks, both of which are common starting points for sequential synthesis and verification tools.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>