Hardware Acceleration Technique Research Articles

Optimizing Hardware Resource Utilization for Accelerating the NTRU-KEM Algorithm

This paper focuses on enhancing the performance of the Nth-degree truncated-polynomial ring units key encapsulation mechanism (NTRU-KEM) algorithm, which ensures post-quantum resistance in the field of key establishment cryptography. The NTRU-KEM, while robust, suffers from increased storage and computational demands compared to classical cryptography, leading to significant memory and performance overheads. In environments with limited resources, the negative impacts of these overheads are more noticeable, leading researchers to investigate ways to speed up processes while also ensuring they are efficient in terms of area utilization. To address this, our research carefully examines the detailed functions of the NTRU-KEM algorithm, adopting a software/hardware co-design approach. This approach allows for customized computation, adapting to the varying requirements of operational timings and iterations. The key contribution is the development of a novel hardware acceleration technique focused on optimizing bus utilization. This technique enables parallel processing of multiple sub-functions, enhancing the overall efficiency of the system. Furthermore, we introduce a unique integrated register array that significantly reduces the spatial footprint of the design by merging multiple registers within the accelerator. In experiments conducted, the results of our work were found to be remarkable, with a time-area efficiency achieved that surpasses previous work by an average of 25.37 times. This achievement underscores the effectiveness of our optimization in accelerating the NTRU-KEM algorithm.

Accelerating generalized linear models with MLWeaving

Learning from the data stored in a database is an important function increasingly available in relational engines. Methods using lower precision input data are of special interest given their overall higher efficiency. However, in databases, these methods have a hidden cost: the quantization of the real value into a smaller number is an expensive step. To address this issue, we present ML-Weaving, a data structure and hardware acceleration technique intended to speed up learning of generalized linear models over low precision data. MLWeaving provides a compact in-memory representation that enables the retrieval of data at any level of precision. MLWeaving also provides a highly efficient implementation of stochastic gradient descent on FPGAs and enables the dynamic tuning of precision, instead of using a fixed precision level during learning. Experimental results show that MLWeaving converges up to 16 x faster than low-precision implementations of first-order methods on CPUs.

The Efficient High‐Resolution SAR Reconstruction Imaging Algorithms for Three‐Dimensional Electrically Large‐Scale Targets in Clutter

AbstractIn recent years, significant effort of both the scientific and industrial community is invested in research and development of multifrequency, multipolarization, and high‐resolution synthetic aperture radar (SAR) systems. One of the key issues is to realize efficient methods for imaging, reconstruction, and target detection of three‐dimensional (3‐D) electrically large‐scale objects. In this paper, an advanced multiple‐input multiple‐output (MIMO) SAR based on high‐resolution imaging algorithm was developed. Specifically, a reasonable sea surface model to quantify the influence of physical parameters in clutter was yielded as well. The SAR simulation system includes the following: (i) refined geometric‐electromagnetic modeling by Gmsh, (ii) a dynamic sea surface model, (iii) single‐input multiple‐output (SIMO) radar imaging formation by employing a fast backprojection algorithm, (iv) design of MIMO antenna arrays to achieve a good trade‐off between the main beam width and the side lobe level, (v) 3‐D SAR imaging algorithm on the basis of optimized physical optics for electromagnetic scattering computation, and (vi) hardware acceleration technique using graphics processing unit. Finally, numerical experiments indicate that 3‐D visualization of sphere, and examples of fighter aircraft and aircraft carrier are generated within 200 s, further proving correctness and effectiveness of the developed 3‐D MIMO SAR imaging algorithm.

The Application of Improved Spherical Harmonics Expansion-Based Multilevel Fast Multipole Algorithm in the Solution of Volume-Surface Integral Equation

During the solution of volume-surface integral equation (VSIE), to reduce the core memory requirement of the radiation patterns (RPs) of the basis functions, an improved spherical harmonics expansion-based multilevel fast multipole algorithm (SE-MLFMA) using the mixed-potential representation and the triangle-/tetrahedron-based grouping scheme is applied. Numerical results show that accompanying with a faster speed, the memory requirement of the RPs in the improved SE-MLFMA is several times less than that in the conventional MLFMA without compromising accuracy. A result employing the OpenMP parallelization and vector arithmetic logic unit (VALU) hardware acceleration technique is also shown to illustrate the robustness and scalability of the improved SE-MLFMA method.

Hardware Acceleration Technique for Radio Resource Scheduling in 5G Mobile Systems

Hardware Acceleration Technique for Radio Resource Scheduling in 5G Mobile Systems

A high performance hardware accelerator for dynamic texture segmentation

The major contribution of this paper is the development of a hardware (FPGA) software (CPU) co-design architecture for accelerating the application of Dynamic Texture Segmentation.This work presents a FPGA implementation of FFT processing sub-system including FFT/IFFT processors, read/write control modules, and memory/FIFO modules, as well as memory optimization using local FIFOs to minimize external RAM access. Such FPGA implementation fully exploits the hardware acceleration technique. All FFT and related operations are executed in hardware which should run orders of magnitude faster than the software implementation.This paper demonstrates that the FPGA-CPU based solution is 37.3 times faster in data processing time and 5.9 times faster in total run time, compared to the CPU (CPU-GPU) based solution. Hardware accelerators such as general-purpose GPUs and FPGAs have been used as an alternative to conventional CPU architectures in scientific computing applications, and have achieved good speed-up results. Within this context, the present study presents a heterogeneous architecture for high-performance computing based on CPUs and FPGAs, which efficiently explores the maximum parallelism degree for processing video segmentation using the concept of dynamic textures. The video segmentation algorithm includes processing the 3-D FFT, calculating the phase spectrum and the 2-D IFFT operation. The performance of the proposed architecture based on CPU and FPGA is compared with the reference implementation of FFTW in CPU and with the cuFFT library in GPU. The performance report of the prototyped architecture in a single Stratix IV FPGA obtained an overall speedup of 37x over the FFTW software library.

Enhanced Parallel FDTD Method Using SSE Instruction Sets

To accelerate the simulation of the parallel FDTD method, this paper proposes an effective hardware acceleration technique based on the SSE instruction sets, and puts forward a three-level data parallel algorithm based on MPI, OpenMP and SSE instructions. To demonstrate the acceleration effect of this technique, this paper develops two types of codes using C language: one is based on MPI + OpenMP, another is based on MPI + OpenMP + SSE, and then draws a comparison between the computing time of the two types of codes in the numerical experiments for the same electromagnetic radiation problems. The experimental results show that this acceleration technique can achieve an acceleration rate of 2.44 for the ideal case on a PC cluster and 2.37 for the practical problem on a 2-CPU workstation without requiring any extra hardware investment, and provide an efficient and economical technique for the electromagnetic simulations.

A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.

Multilevel fast multipole algorithm enhanced by GPU parallel technique for electromagnetic scattering problems

AbstractAlong with the development of graphics processing Units (GPUS) in floating point operations and programmability, GPU has increasingly become an attractive alternative to the central processing unit (CPU) for some of compute‐intensive and parallel tasks.In this article, the multilevel fast multipole algorithm (MLFMA) combined with graphics hardware acceleration technique is applied to analyze electromagnetic scattering from complex target. Although it is possible to perform scattering simulation of electrically large targets on a personal computer (PC) through the MLFMA, a large CPU time is required for the execution of aggregation, translation, and deaggregation operations. Thus GPU computing technique is used for the parallel processing of MLFMA and a significant speedup of matrix vector product (MVP) can be observed. Following the programming model of compute unified device architecture (CUDA), several kernel functions characterized by the single instruction multiple data (SIMD) mode are abstracted from components of the MLFMA and executed by multiple processors of the GPU. Numerical results demonstrate the efficiency of GPU accelerating technique for the MLFMA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 502–507, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24963